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| author | Joachim Eastwood <manabian@gmail.com> | 2015-08-09 00:02:41 +0200 |
|---|---|---|
| committer | Kishon Vijay Abraham I <kishon@ti.com> | 2015-08-10 20:11:58 +0530 |
| commit | cfd093bbb5fe84ec8c7bb069fe618159a8b601f5 (patch) | |
| tree | 79774b2538a63a49374d9fc11e7805166ed0fe12 /drivers/phy | |
| parent | 4a9e5ca1a54a3cb4a5f85359f646638cec567607 (diff) | |
| download | linux-stable-cfd093bbb5fe84ec8c7bb069fe618159a8b601f5.tar.gz linux-stable-cfd093bbb5fe84ec8c7bb069fe618159a8b601f5.tar.bz2 linux-stable-cfd093bbb5fe84ec8c7bb069fe618159a8b601f5.zip | |
phy: lpc18xx-usb-otg: fix clock order in phy init
Changing the frequency of the USB clock must be done before the
PLL is powered on (prepared). This matters when the USB clock
is not setup by either boot ROM or boot loader. Reorder the
function calls to adhere to the order noted in the user manual.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/phy-lpc18xx-usb-otg.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/phy/phy-lpc18xx-usb-otg.c b/drivers/phy/phy-lpc18xx-usb-otg.c index 3aa8e4de1b03..3b7a71eb5b7e 100644 --- a/drivers/phy/phy-lpc18xx-usb-otg.c +++ b/drivers/phy/phy-lpc18xx-usb-otg.c @@ -33,12 +33,12 @@ static int lpc18xx_usb_otg_phy_init(struct phy *phy) struct lpc18xx_usb_otg_phy *lpc = phy_get_drvdata(phy); int ret; - ret = clk_prepare(lpc->clk); + /* The PHY must be clocked at 480 MHz */ + ret = clk_set_rate(lpc->clk, 480000000); if (ret) return ret; - /* The PHY must be clocked at 480 MHz */ - return clk_set_rate(lpc->clk, 480000000); + return clk_prepare(lpc->clk); } static int lpc18xx_usb_otg_phy_exit(struct phy *phy) |