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authorDmitry Rokosov <ddrokosov@sberdevices.ru>2023-04-26 13:29:18 +0300
committerVinod Koul <vkoul@kernel.org>2023-05-08 14:57:37 +0530
commit58247b9fedd6d7f7dcbeaf6bb57fd7a99403a1bb (patch)
treebbe2d13dccd84861d1c682a5215dcb2d82e96f92 /drivers/phy
parentac9a78681b921877518763ba0e89202254349d1b (diff)
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phy: amlogic: enable/disable clkin during Amlogic USB PHY init/exit
Previously, all Amlogic boards used the XTAL clock as the default board clock for the USB PHY input, so there was no need to enable it. However, with the introduction of new Amlogic SoCs like the A1 family, the USB PHY now uses a gated clock. Hence, it is necessary to enable this gated clock during the PHY initialization sequence, or disable it during the PHY exit, as appropriate. Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230426102922.19705-2-ddrokosov@sberdevices.ru Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/amlogic/phy-meson-g12a-usb2.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
index 9d1efa0d9394..ec2555bb83d5 100644
--- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c
+++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
@@ -172,10 +172,16 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
int ret;
unsigned int value;
- ret = reset_control_reset(priv->reset);
+ ret = clk_prepare_enable(priv->clk);
if (ret)
return ret;
+ ret = reset_control_reset(priv->reset);
+ if (ret) {
+ clk_disable_unprepare(priv->clk);
+ return ret;
+ }
+
udelay(RESET_COMPLETE_TIME);
/* usb2_otg_aca_en == 0 */
@@ -277,8 +283,13 @@ static int phy_meson_g12a_usb2_init(struct phy *phy)
static int phy_meson_g12a_usb2_exit(struct phy *phy)
{
struct phy_meson_g12a_usb2_priv *priv = phy_get_drvdata(phy);
+ int ret;
+
+ ret = reset_control_reset(priv->reset);
+ if (!ret)
+ clk_disable_unprepare(priv->clk);
- return reset_control_reset(priv->reset);
+ return ret;
}
/* set_mode is not needed, mode setting is handled via the UTMI bus */