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authorWolfram Sang <wsa+renesas@sang-engineering.com>2016-03-02 23:57:09 +0100
committerThierry Reding <thierry.reding@gmail.com>2016-03-23 17:11:29 +0100
commit0e47b5981a30e856c9c4aba785890528486d1594 (patch)
tree346bdb50ebdc9bbfc02a93ed2a18012f2b73e10d /drivers/pwm
parentbea307c16a3a297f87c7ab9a54de686da2afbad5 (diff)
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pwm: lpc18xx-sct: Test clock rate to avoid division by 0
The clk API may return 0 on clk_get_rate(), so we should check the result before using it as a divisor. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Diffstat (limited to 'drivers/pwm')
-rw-r--r--drivers/pwm/pwm-lpc18xx-sct.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/pwm/pwm-lpc18xx-sct.c b/drivers/pwm/pwm-lpc18xx-sct.c
index 9163085101bc..9861fed4e67d 100644
--- a/drivers/pwm/pwm-lpc18xx-sct.c
+++ b/drivers/pwm/pwm-lpc18xx-sct.c
@@ -360,6 +360,11 @@ static int lpc18xx_pwm_probe(struct platform_device *pdev)
}
lpc18xx_pwm->clk_rate = clk_get_rate(lpc18xx_pwm->pwm_clk);
+ if (!lpc18xx_pwm->clk_rate) {
+ dev_err(&pdev->dev, "pwm clock has no frequency\n");
+ ret = -EINVAL;
+ goto disable_pwmclk;
+ }
mutex_init(&lpc18xx_pwm->res_lock);
mutex_init(&lpc18xx_pwm->period_lock);