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authorYang Yingliang <yangyingliang@huawei.com>2022-10-18 10:31:48 +0800
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2022-12-31 13:31:50 +0100
commit0883dc428c95c123228a4acf340ff21ce5bdd8a3 (patch)
tree1a04bd7f587dc33de2b7d2a5c846faf663abdf5c /drivers/soc
parent7ea9128d1a91001edd954dd1b8cf5666145ddafe (diff)
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soc: sifive: ccache: fix missing free_irq() in error path in sifive_ccache_init()
[ Upstream commit 756344e7cb1afbb87da8705c20384dddd0dea233 ] Add missing free_irq() before return error from sifive_ccache_init(). Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/sifive/sifive_ccache.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
index 25019c16d8ae..98269d056728 100644
--- a/drivers/soc/sifive/sifive_ccache.c
+++ b/drivers/soc/sifive/sifive_ccache.c
@@ -240,7 +240,7 @@ static int __init sifive_ccache_init(void)
NULL);
if (rc) {
pr_err("Could not request IRQ %d\n", g_irq[i]);
- goto err_unmap;
+ goto err_free_irq;
}
}
@@ -254,6 +254,9 @@ static int __init sifive_ccache_init(void)
#endif
return 0;
+err_free_irq:
+ while (--i >= 0)
+ free_irq(g_irq[i], NULL);
err_unmap:
iounmap(ccache_base);
return rc;