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| author | Serge Semin <Sergey.Semin@baikalelectronics.ru> | 2020-10-08 02:55:07 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-10-08 23:00:20 +0100 |
| commit | 84ecaf4a7837e8c0957a59d77fd7e8e4926968cb (patch) | |
| tree | ed78ba24895c4dff440107243b11f1556d4b0305 /drivers/spi/spi-dw-core.c | |
| parent | 6423207e57ea53826eaae1a14c14fd6d22561b06 (diff) | |
| download | linux-stable-84ecaf4a7837e8c0957a59d77fd7e8e4926968cb.tar.gz linux-stable-84ecaf4a7837e8c0957a59d77fd7e8e4926968cb.tar.bz2 linux-stable-84ecaf4a7837e8c0957a59d77fd7e8e4926968cb.zip | |
spi: dw: Introduce max mem-ops SPI bus frequency setting
In some circumstances the current implementation of the SPI memory
operations may occasionally fail even though they are executed in the
atomic context. This may happen if the system bus is relatively slow in
comparison to the SPI bus frequency, or there is a concurrent access to
it, which makes the MMIO-operations occasionally stalling before
push-pulling data from the DW APB SPI FIFOs. These two problems we've
discovered on the Baikal-T1 SoC. In order to fix them we have no choice
but to set an artificial limitation on the SPI bus speed.
Note currently this limitation will be only applicable for the memory
operations, since the standard SPI core interface is implemented with an
assumption that there is no problem with the automatic CS toggling.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Link: https://lore.kernel.org/r/20201007235511.4935-19-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-dw-core.c')
| -rw-r--r-- | drivers/spi/spi-dw-core.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 8eb3b31b376d..bcfa224e0e43 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -629,7 +629,7 @@ static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op) * operation. Transmit-only mode is suitable for the rest of them. */ cfg.dfs = 8; - cfg.freq = mem->spi->max_speed_hz; + cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq); if (op->data.dir == SPI_MEM_DATA_IN) { cfg.tmode = SPI_TMOD_EPROMREAD; cfg.ndf = op->data.nbytes; @@ -717,6 +717,8 @@ static void dw_spi_init_mem_ops(struct dw_spi *dws) dws->mem_ops.adjust_op_size = dw_spi_adjust_mem_op_size; dws->mem_ops.supports_op = dw_spi_supports_mem_op; dws->mem_ops.exec_op = dw_spi_exec_mem_op; + if (!dws->max_mem_freq) + dws->max_mem_freq = dws->max_freq; } } |