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| author | Vignesh R <vigneshr@ti.com> | 2019-01-15 12:28:32 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-12-01 09:17:33 +0100 |
| commit | 1efa17ab9cb830119b5f456b5f0a37aa3f44adbe (patch) | |
| tree | 71ec1b140eea6e371a2e6fbfe9b6c983c7c08fad /drivers/spi | |
| parent | 1b0f1b2dde066c8dd78c9df9e33c82eecf572dcc (diff) | |
| download | linux-stable-1efa17ab9cb830119b5f456b5f0a37aa3f44adbe.tar.gz linux-stable-1efa17ab9cb830119b5f456b5f0a37aa3f44adbe.tar.bz2 linux-stable-1efa17ab9cb830119b5f456b5f0a37aa3f44adbe.zip | |
spi: omap2-mcspi: Fix DMA and FIFO event trigger size mismatch
[ Upstream commit baf8b9f8d260c55a86405f70a384c29cda888476 ]
Commit b682cffa3ac6 ("spi: omap2-mcspi: Set FIFO DMA trigger level to word length")
broke SPI transfers where bits_per_word != 8. This is because of
mimsatch between McSPI FIFO level event trigger size (SPI word length) and
DMA request size(word length * maxburst). This leads to data
corruption, lockup and errors like:
spi1.0: EOW timed out
Fix this by setting DMA maxburst size to 1 so that
McSPI FIFO level event trigger size matches DMA request size.
Fixes: b682cffa3ac6 ("spi: omap2-mcspi: Set FIFO DMA trigger level to word length")
Cc: stable@vger.kernel.org
Reported-by: David Lechner <david@lechnology.com>
Tested-by: David Lechner <david@lechnology.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-omap2-mcspi.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c index f50cb8a4b413..eb2d2de172af 100644 --- a/drivers/spi/spi-omap2-mcspi.c +++ b/drivers/spi/spi-omap2-mcspi.c @@ -607,8 +607,8 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer) cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0; cfg.src_addr_width = width; cfg.dst_addr_width = width; - cfg.src_maxburst = es; - cfg.dst_maxburst = es; + cfg.src_maxburst = 1; + cfg.dst_maxburst = 1; rx = xfer->rx_buf; tx = xfer->tx_buf; |