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| author | Artur Petrosyan <Arthur.Petrosyan@synopsys.com> | 2021-04-08 13:45:49 +0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-05-22 10:59:22 +0200 |
| commit | a32ccf93f257ca5c515ddb8a2fb8750f442ffca0 (patch) | |
| tree | 2a054d1e80d4b31646cf39c8cce92f6ada6fc5c5 /drivers/usb/dwc2 | |
| parent | be9997ba10009b6634e3fd90c33cd3d6899e1298 (diff) | |
| download | linux-stable-a32ccf93f257ca5c515ddb8a2fb8750f442ffca0.tar.gz linux-stable-a32ccf93f257ca5c515ddb8a2fb8750f442ffca0.tar.bz2 linux-stable-a32ccf93f257ca5c515ddb8a2fb8750f442ffca0.zip | |
usb: dwc2: Fix session request interrupt handler
commit 42b32b164acecd850edef010915a02418345a033 upstream.
According to programming guide in host mode, port
power must be turned on in session request
interrupt handlers.
Fixes: 21795c826a45 ("usb: dwc2: exit hibernation on session request")
Cc: <stable@vger.kernel.org>
Acked-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com>
Signed-off-by: Artur Petrosyan <Arthur.Petrosyan@synopsys.com>
Link: https://lore.kernel.org/r/20210408094550.75484A0094@mailhost.synopsys.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/usb/dwc2')
| -rw-r--r-- | drivers/usb/dwc2/core_intr.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c index b23ce535c12e..14efa28e048f 100644 --- a/drivers/usb/dwc2/core_intr.c +++ b/drivers/usb/dwc2/core_intr.c @@ -312,6 +312,7 @@ static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) { int ret; + u32 hprt0; /* Clear interrupt */ dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS); @@ -332,6 +333,13 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) * established */ dwc2_hsotg_disconnect(hsotg); + } else { + /* Turn on the port power bit. */ + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_PWR; + dwc2_writel(hsotg, hprt0, HPRT0); + /* Connect hcd after port power is set. */ + dwc2_hcd_connect(hsotg); } } |