diff options
author | Huang Rui <ray.huang@amd.com> | 2014-10-28 19:54:35 +0800 |
---|---|---|
committer | Felipe Balbi <balbi@ti.com> | 2014-11-03 10:03:38 -0600 |
commit | 2164a476205ccc62c5874f95f3504b657fff5c04 (patch) | |
tree | 6ddb9220c0e77851c50891f4cbbaa046a26e973a /drivers/usb/dwc3 | |
parent | 14f4ac53dfb2321b07a0e690df797fba61102fa6 (diff) | |
download | linux-stable-2164a476205ccc62c5874f95f3504b657fff5c04.tar.gz linux-stable-2164a476205ccc62c5874f95f3504b657fff5c04.tar.bz2 linux-stable-2164a476205ccc62c5874f95f3504b657fff5c04.zip |
usb: dwc3: set SUSPHY bit for all cores
It is recommended to set USB3 and USB2 SUSPHY bits to '1' after the core
initialization is completed above the dwc3 revision 1.94a.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Diffstat (limited to 'drivers/usb/dwc3')
-rw-r--r-- | drivers/usb/dwc3/core.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index b440b2b29872..aefb59d6db8f 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -374,6 +374,15 @@ static void dwc3_phy_setup(struct dwc3 *dwc) reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + /* + * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY + * to '0' during coreConsultant configuration. So default value + * will be '0' when the core is reset. Application needs to set it + * to '1' after the core initialization is completed. + */ + if (dwc->revision > DWC3_REVISION_194A) + reg |= DWC3_GUSB3PIPECTL_SUSPHY; + if (dwc->u2ss_inp3_quirk) reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK; @@ -395,6 +404,21 @@ static void dwc3_phy_setup(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); mdelay(100); + + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + + /* + * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to + * '0' during coreConsultant configuration. So default value will + * be '0' when the core is reset. Application needs to set it to + * '1' after the core initialization is completed. + */ + if (dwc->revision > DWC3_REVISION_194A) + reg |= DWC3_GUSB2PHYCFG_SUSPHY; + + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + + mdelay(100); } /** |