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authorMatt Redfearn <matt.redfearn@imgtec.com>2016-06-14 14:59:38 +0100
committerRalf Baechle <ralf@linux-mips.org>2016-08-03 09:01:48 +0200
commit4f53989b0652ffe2605221c81ca8ffcfc90aed2a (patch)
tree2745a85b98ae8dd871db4edc34149e2eca0075a6 /drivers
parent828a54287c09fea6cd2102b7764d9a10f50bc44d (diff)
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MIPS: mm: Fix definition of R6 cache instruction
Commit a168b8f1cde6 ("MIPS: mm: Add MIPS R6 instruction encodings") added an incorrect definition of the redefined MIPSr6 cache instruction. Executing any kernel code including this instuction results in a reserved instruction exception and kernel panic. Fix the instruction definition. Fixes: a168b8f1cde6588ff7a67699fa11e01bc77a5ddd Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Cc: <stable@vger.kernel.org> # 4.x- Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13663/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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