diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2010-04-12 06:58:24 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-04-13 02:25:42 -0700 |
| commit | cea46462681d61a65a208d17206d38739c1ea1b1 (patch) | |
| tree | af5b17960d6871e9dc2b6d104eaadf87730220f5 /drivers | |
| parent | b6c6712a42ca3f9fa7f4a3d7c40e3a9dd1fd9e03 (diff) | |
| download | linux-stable-cea46462681d61a65a208d17206d38739c1ea1b1.tar.gz linux-stable-cea46462681d61a65a208d17206d38739c1ea1b1.tar.bz2 linux-stable-cea46462681d61a65a208d17206d38739c1ea1b1.zip | |
tg3: Disable CLKREQ in L2
This patch disables CLKREQ in L2 to workaround a chipset bug.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/tg3.c | 14 | ||||
| -rw-r--r-- | drivers/net/tg3.h | 2 |
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 460a0c22b318..4ae01b3799f4 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -7642,6 +7642,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) tw32(GRC_MODE, grc_mode); } + if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { + u32 grc_mode = tr32(GRC_MODE); + + /* Access the lower 1K of PL PCIE block registers. */ + val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; + tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); + + val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5); + tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, + val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); + + tw32(GRC_MODE, grc_mode); + } + /* This works around an issue with Athlon chipsets on * B3 tigon3 silicon. This bit has no effect on any * other revision. But do not set this on PCI Express diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 5d7f72a2ea01..8a6012ab23ff 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -1854,6 +1854,8 @@ #define TG3_PCIE_TLDLPL_PORT 0x00007c00 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 +#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 +#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 /* OTP bit definitions */ #define TG3_OTP_AGCTGT_MASK 0x000000e0 |