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| author | Nishanth Menon <nm@ti.com> | 2014-05-16 05:45:59 -0500 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2014-06-06 20:33:39 +0300 |
| commit | b4be018921879ba7452379af8fb7320833a12bd4 (patch) | |
| tree | a86e2a290ed68da325bf1f623b6b4437ca4d1771 /drivers | |
| parent | ce369a545aac3da653dd95d8117093a862bf94d3 (diff) | |
| download | linux-stable-b4be018921879ba7452379af8fb7320833a12bd4.tar.gz linux-stable-b4be018921879ba7452379af8fb7320833a12bd4.tar.bz2 linux-stable-b4be018921879ba7452379af8fb7320833a12bd4.zip | |
CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies
MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum
frequency it can be locked at. Duty Cycle Correction circuit is used
to recover a correct duty cycle for achieving higher frequencies
(hardware internally switches output to M3 output(CLKOUTHIF) from M2
output (CLKOUT)).
So provide support to setup required data to handle Duty cycle by
the setting up the minimum frequency for DPLL. 1.4GHz is common
for all these devices and is based on Technical Reference Manual
information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output
Clocks Parameters", and equivalent information from DRA75x, DRA72x
documentation(SPRUHP2E, SPRUHI2P).
Signed-off-by: Nishanth Menon <nm@ti.com>
[t-kristo@ti.com: updated for latest dpll init API call]
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/ti/dpll.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index 34e233990212..abd956d5f838 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -433,6 +433,27 @@ static void __init of_ti_omap4_dpll_setup(struct device_node *node) CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock", of_ti_omap4_dpll_setup); +static void __init of_ti_omap5_mpu_dpll_setup(struct device_node *node) +{ + const struct dpll_data dd = { + .idlest_mask = 0x1, + .enable_mask = 0x7, + .autoidle_mask = 0x7, + .mult_mask = 0x7ff << 8, + .div1_mask = 0x7f, + .max_multiplier = 2047, + .max_divider = 128, + .dcc_mask = BIT(22), + .dcc_rate = 1400000000, /* DCC beyond 1.4GHz */ + .min_divider = 1, + .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), + }; + + of_ti_dpll_setup(node, &dpll_ck_ops, &dd); +} +CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock", + of_ti_omap5_mpu_dpll_setup); + static void __init of_ti_omap4_core_dpll_setup(struct device_node *node) { const struct dpll_data dd = { |