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| author | Bjorn Helgaas <bhelgaas@google.com> | 2012-12-26 10:39:23 -0700 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2012-12-26 10:39:23 -0700 |
| commit | 130f1b8f35f14d27c43da755f3c9226318c17f57 (patch) | |
| tree | 40429fe6acb8aed6729db8e3016bf036c0078e1e /drivers | |
| parent | 1278998f8ff6d66044ed00b581bbf14aacaba215 (diff) | |
| download | linux-stable-130f1b8f35f14d27c43da755f3c9226318c17f57.tar.gz linux-stable-130f1b8f35f14d27c43da755f3c9226318c17f57.tar.bz2 linux-stable-130f1b8f35f14d27c43da755f3c9226318c17f57.zip | |
PCI: Add PCIe Link Capability link speed and width names
Add standard #defines for the Supported Link Speeds field in the PCIe
Link Capabilities register.
Note that prior to PCIe spec r3.0, these encodings were defined:
0001b 2.5GT/s Link speed supported
0010b 5.0GT/s and 2.5GT/s Link speed supported
Starting with spec r3.0, these encodings refer to bits 0 and 1 in the
Supported Link Speeds Vector in the Link Capabilities 2 register, and bits
0 and 1 there mean 2.5 GT/s and 5.0 GT/s, respectively. Therefore, code
that followed r2.0 and interpreted 0x1 as 2.5GT/s and 0x2 as 5.0GT/s will
continue to work, and we can identify a device using the new encodings
because it will have a non-zero Link Capabilities 2 register.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers')
0 files changed, 0 insertions, 0 deletions