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| author | Satya Priya Kakitapalli <quic_skakitap@quicinc.com> | 2024-07-31 11:59:09 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-07-31 21:56:09 -0500 |
| commit | 2c4553e6c485a96b5d86989eb9654bf20e51e6dd (patch) | |
| tree | f995002f8d00397995876ab0a67d2aadee7bd608 /drivers | |
| parent | 8400291e289ee6b2bf9779ff1c83a291501f017b (diff) | |
| download | linux-stable-2c4553e6c485a96b5d86989eb9654bf20e51e6dd.tar.gz linux-stable-2c4553e6c485a96b5d86989eb9654bf20e51e6dd.tar.bz2 linux-stable-2c4553e6c485a96b5d86989eb9654bf20e51e6dd.zip | |
clk: qcom: clk-alpha-pll: Fix the pll post div mask
The PLL_POST_DIV_MASK should be 0 to (width - 1) bits. Fix it.
Fixes: 1c3541145cbf ("clk: qcom: support for 2 bit PLL post divider")
Cc: stable@vger.kernel.org
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
Link: https://lore.kernel.org/r/20240731062916.2680823-2-quic_skakitap@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/qcom/clk-alpha-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index d87314042528..9ce45cd6e09f 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -40,7 +40,7 @@ #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) # define PLL_POST_DIV_SHIFT 8 -# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0) +# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0) # define PLL_ALPHA_EN BIT(24) # define PLL_ALPHA_MODE BIT(25) # define PLL_VCO_SHIFT 20 |