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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2022-06-29 01:17:44 +0300 |
|---|---|---|
| committer | Lee Jones <lee@kernel.org> | 2022-07-19 10:54:42 +0100 |
| commit | f801556a8443f38b10f87fe8dc847dacff3f1a0a (patch) | |
| tree | 8af89e0c466ee69c092e005cc46115e3d457a9b2 /drivers | |
| parent | cd58c84034234a51bdb852a862f9037b68622d45 (diff) | |
| download | linux-stable-f801556a8443f38b10f87fe8dc847dacff3f1a0a.tar.gz linux-stable-f801556a8443f38b10f87fe8dc847dacff3f1a0a.tar.bz2 linux-stable-f801556a8443f38b10f87fe8dc847dacff3f1a0a.zip | |
mfd: intel_soc_pmic_bxtwc: Use bits.h macros for all masks
Currently we are using BIT(), but GENMASK(). Make use of the latter one
as well (far less error-prone, far more concise).
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20220628221747.33956-8-andriy.shevchenko@linux.intel.com
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mfd/intel_soc_pmic_bxtwc.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/drivers/mfd/intel_soc_pmic_bxtwc.c b/drivers/mfd/intel_soc_pmic_bxtwc.c index f79ae0ddc495..5ac623eda1c1 100644 --- a/drivers/mfd/intel_soc_pmic_bxtwc.c +++ b/drivers/mfd/intel_soc_pmic_bxtwc.c @@ -6,6 +6,7 @@ */ #include <linux/acpi.h> +#include <linux/bits.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/interrupt.h> @@ -18,9 +19,9 @@ #include <asm/intel_scu_ipc.h> /* PMIC device registers */ -#define REG_ADDR_MASK 0xFF00 +#define REG_ADDR_MASK GENMASK(15, 8) #define REG_ADDR_SHIFT 8 -#define REG_OFFSET_MASK 0xFF +#define REG_OFFSET_MASK GENMASK(7, 0) /* Interrupt Status Registers */ #define BXTWC_IRQLVL1 0x4E02 @@ -112,29 +113,29 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = { }; static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = { - REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, 0x01), + REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, BIT(0)), }; static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = { - REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f), + REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)), }; static const struct regmap_irq bxtwc_regmap_irqs_adc[] = { - REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff), + REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)), }; static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = { - REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, 0x20), - REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f), - REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f), + REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)), + REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)), + REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)), }; static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = { - REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06), + REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)), }; static const struct regmap_irq bxtwc_regmap_irqs_crit[] = { - REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03), + REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)), }; static struct regmap_irq_chip bxtwc_regmap_irq_chip = { |