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authorDinh Nguyen <dinguyen@kernel.org>2019-08-14 10:30:14 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2019-08-29 08:30:21 +0200
commite9e5f8e96fe63dbf4b023e1d9ff7cd4fd5fd810e (patch)
treee11f1a66d9540f348fde621b8c2db9d6d6d88e90 /fs
parent328380940d3ab433ee3d60451cb6072cb041b76b (diff)
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clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
commit c7ec75ea4d5316518adc87224e3cff47192579e7 upstream. Checking bypass_reg is incorrect for calculating the cnt_clk rates. Instead we should be checking that there is a proper hardware register that holds the clock divider. Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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