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| author | Ralf Baechle <ralf@linux-mips.org> | 2005-12-08 13:00:20 +0000 |
|---|---|---|
| committer | <ralf@denk.linux-mips.net> | 2006-01-10 13:39:06 +0000 |
| commit | e7958bb90d57f0da073cbd031a1808de51d1de15 (patch) | |
| tree | b4f0d57ab157c64ce23722dbd29864901794a019 /include/asm-mips/cpu.h | |
| parent | 571e0bed85470882cedfb100e847902911c3f4d2 (diff) | |
| download | linux-stable-e7958bb90d57f0da073cbd031a1808de51d1de15.tar.gz linux-stable-e7958bb90d57f0da073cbd031a1808de51d1de15.tar.bz2 linux-stable-e7958bb90d57f0da073cbd031a1808de51d1de15.zip | |
MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu.h')
| -rw-r--r-- | include/asm-mips/cpu.h | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 48eac296060f..256fe130eae8 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -202,18 +202,15 @@ * ISA Level encodings * */ +#define MIPS_CPU_ISA_64BIT 0x00008000 + #define MIPS_CPU_ISA_I 0x00000001 #define MIPS_CPU_ISA_II 0x00000002 -#define MIPS_CPU_ISA_III 0x00008003 -#define MIPS_CPU_ISA_IV 0x00008004 -#define MIPS_CPU_ISA_V 0x00008005 -#define MIPS_CPU_ISA_M32 0x00000020 -#define MIPS_CPU_ISA_M64 0x00008040 - -/* - * Bit 15 encodes if an ISA level supports 64-bit operations. - */ -#define MIPS_CPU_ISA_64BIT 0x00008000 +#define MIPS_CPU_ISA_III (0x00000003 | MIPS_CPU_ISA_64BIT) +#define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT) +#define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT) +#define MIPS_CPU_ISA_M32R1 0x00000020 +#define MIPS_CPU_ISA_M64R1 (0x00000040 | MIPS_CPU_ISA_64BIT) /* * CPU Option encodings |