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| author | Paul Cercueil <paul@crapouillou.net> | 2018-06-27 14:14:59 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-07-06 11:47:28 -0700 |
| commit | 2b555a4b9caecfcab1b2aade176df795ceceaefa (patch) | |
| tree | 669673479270703249ca63368e52ea548a6eb7f6 /include/dt-bindings | |
| parent | 574f4e80d59e5c669c0729718525df8bac5e4d78 (diff) | |
| download | linux-stable-2b555a4b9caecfcab1b2aade176df795ceceaefa.tar.gz linux-stable-2b555a4b9caecfcab1b2aade176df795ceceaefa.tar.bz2 linux-stable-2b555a4b9caecfcab1b2aade176df795ceceaefa.zip | |
clk: ingenic: Add missing flag for UDC clock
The UDC clock of the JZ4740 SoC can be gated, but the data structure
representing it was missing the CGU_CLK_GATE flag to make it work.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings')
0 files changed, 0 insertions, 0 deletions