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author | Andrew Bresticker <abrestic@chromium.org> | 2014-05-14 17:32:59 -0700 |
---|---|---|
committer | Mike Turquette <mturquette@linaro.org> | 2014-05-22 22:14:52 -0700 |
commit | 5c992afcf8e4f91fac05d39b86c7f7922a50145c (patch) | |
tree | 349870dc6143624ca62f5cfa2aa9de3460095d20 /include/dt-bindings | |
parent | 9d61707b1f83324fc30918787cb6ef101997ecbd (diff) | |
download | linux-stable-5c992afcf8e4f91fac05d39b86c7f7922a50145c.tar.gz linux-stable-5c992afcf8e4f91fac05d39b86c7f7922a50145c.tar.bz2 linux-stable-5c992afcf8e4f91fac05d39b86c7f7922a50145c.zip |
clk: tegra: Fix xusb_hs_src clock hierarchy
Currently the Tegra1x4 clock init code hard-codes the mux setting
for xusb_hs_src and treats it as a fixed-factor clock. It is,
however, a mux which can be parented by either xusb_ss_src/2 or
pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an
entry in periph_clks[] for the xusb_hs_src mux.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r-- | include/dt-bindings/clock/tegra114-car.h | 3 | ||||
-rw-r--r-- | include/dt-bindings/clock/tegra124-car.h | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h index 6d0d8d8ef31e..fc12621fb432 100644 --- a/include/dt-bindings/clock/tegra114-car.h +++ b/include/dt-bindings/clock/tegra114-car.h @@ -337,6 +337,7 @@ #define TEGRA114_CLK_CLK_OUT_3_MUX 308 #define TEGRA114_CLK_DSIA_MUX 309 #define TEGRA114_CLK_DSIB_MUX 310 -#define TEGRA114_CLK_CLK_MAX 311 +#define TEGRA114_CLK_XUSB_SS_DIV2 311 +#define TEGRA114_CLK_CLK_MAX 312 #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h index 433528ab5161..8a4c5892890f 100644 --- a/include/dt-bindings/clock/tegra124-car.h +++ b/include/dt-bindings/clock/tegra124-car.h @@ -336,6 +336,7 @@ #define TEGRA124_CLK_DSIA_MUX 309 #define TEGRA124_CLK_DSIB_MUX 310 #define TEGRA124_CLK_SOR0_LVDS 311 -#define TEGRA124_CLK_CLK_MAX 312 +#define TEGRA124_CLK_XUSB_SS_DIV2 312 +#define TEGRA124_CLK_CLK_MAX 313 #endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ |