diff options
| author | Mattias Nilsson <mattias.i.nilsson@stericsson.com> | 2012-01-13 16:20:43 +0100 |
|---|---|---|
| committer | Samuel Ortiz <sameo@linux.intel.com> | 2012-03-06 18:46:33 +0100 |
| commit | 4d64d2e34bc415b05eb77a2732a3164313cf6de3 (patch) | |
| tree | f4331b9e59754a52f83cfc79b6ca1547861a1a89 /include/linux/mfd/dbx500-prcmu.h | |
| parent | 992b133a5d85ced4ff0fbdab22e9196cf571e0c9 (diff) | |
| download | linux-stable-4d64d2e34bc415b05eb77a2732a3164313cf6de3.tar.gz linux-stable-4d64d2e34bc415b05eb77a2732a3164313cf6de3.tar.bz2 linux-stable-4d64d2e34bc415b05eb77a2732a3164313cf6de3.zip | |
mfd: db8500 OPP and sleep handling update
This updates the operating point handling code by:
- Supporting the DDR OPP retention state.
- Supporting another low operating point named
APE_50_PARTLY_25_OPP
- Adding an interface to figure out if the sleep state change
was properly achieved.
Signed-off-by: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'include/linux/mfd/dbx500-prcmu.h')
| -rw-r--r-- | include/linux/mfd/dbx500-prcmu.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h index 8470c7d7121f..432a2d3fc198 100644 --- a/include/linux/mfd/dbx500-prcmu.h +++ b/include/linux/mfd/dbx500-prcmu.h @@ -185,12 +185,14 @@ enum prcmu_clock { * @APE_NO_CHANGE: The APE operating point is unchanged * @APE_100_OPP: The new APE operating point is ape100opp * @APE_50_OPP: 50% + * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. */ enum ape_opp { APE_OPP_INIT = 0x00, APE_NO_CHANGE = 0x01, APE_100_OPP = 0x02, - APE_50_OPP = 0x03 + APE_50_OPP = 0x03, + APE_50_PARTLY_25_OPP = 0xFF, }; /** @@ -271,6 +273,14 @@ static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, keep_ap_pll); } +static inline u8 prcmu_get_power_state_result(void) +{ + if (cpu_is_u5500()) + return -EINVAL; + else + return db8500_prcmu_get_power_state_result(); +} + static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) { if (cpu_is_u5500()) @@ -663,9 +673,10 @@ static inline int prcmu_stop_temp_sense(void) /* PRCMU QoS APE OPP class */ #define PRCMU_QOS_APE_OPP 1 #define PRCMU_QOS_DDR_OPP 2 +#define PRCMU_QOS_ARM_OPP 3 #define PRCMU_QOS_DEFAULT_VALUE -1 -#ifdef CONFIG_UX500_PRCMU_QOS_POWER +#ifdef CONFIG_DBX500_PRCMU_QOS_POWER unsigned long prcmu_qos_get_cpufreq_opp_delay(void); void prcmu_qos_set_cpufreq_opp_delay(unsigned long); |