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| author | Daniel Mack <zonque@gmail.com> | 2012-12-10 10:30:04 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2012-12-24 15:53:28 +0000 |
| commit | fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3 (patch) | |
| tree | a1033cbc88a3ccba164e8d0f6c7469f9efd6713a /include/sound/cs4271.h | |
| parent | 133d2e6188de86df3ed84cd42ac66e9c5d328c04 (diff) | |
| download | linux-stable-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.tar.gz linux-stable-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.tar.bz2 linux-stable-fd23fb9f6bfd43a6e62b2646d18d5ca3edc3ebe3.zip | |
ALSA: ASoC: cs4271: add optional soft reset workaround
The CS4271 requires its LRCLK and MCLK to be stable before its RESET
line is de-asserted. That also means that clocks cannot be changed
without putting the chip back into hardware reset, which also requires
a complete re-initialization of all registers.
One (undocumented) workaround is to assert and de-assert the PDN bit
in the MODE2 register.
This patch adds a new flag to both the DT bindings as well as to the
platform data to enable that workaround.
Signed-off-by: Daniel Mack <zonque@gmail.com>
Acked-by: Alexander Sverdlin <subaparts@yandex.ru>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'include/sound/cs4271.h')
| -rw-r--r-- | include/sound/cs4271.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/sound/cs4271.h b/include/sound/cs4271.h index dd8c48d14ed9..70f45355acaa 100644 --- a/include/sound/cs4271.h +++ b/include/sound/cs4271.h @@ -20,6 +20,21 @@ struct cs4271_platform_data { int gpio_nreset; /* GPIO driving Reset pin, if any */ bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ + + /* + * The CS4271 requires its LRCLK and MCLK to be stable before its RESET + * line is de-asserted. That also means that clocks cannot be changed + * without putting the chip back into hardware reset, which also requires + * a complete re-initialization of all registers. + * + * One (undocumented) workaround is to assert and de-assert the PDN bit + * in the MODE2 register. This workaround can be enabled with the + * following flag. + * + * Note that this is not needed in case the clocks are stable + * throughout the entire runtime of the codec. + */ + bool enable_soft_reset; }; #endif /* __CS4271_H */ |