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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-08-10 14:51:11 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-08-22 13:31:34 +0200 |
| commit | 35c7ab421a13f8327e3fd627c6ebafb1c13b2e55 (patch) | |
| tree | 18cb8bab96e8158ca71f0b311250fa0eb475a8f6 /include/uapi/drm | |
| parent | 000433b67e46771a7c08f78574943855a98c53ec (diff) | |
| download | linux-stable-35c7ab421a13f8327e3fd627c6ebafb1c13b2e55.tar.gz linux-stable-35c7ab421a13f8327e3fd627c6ebafb1c13b2e55.tar.bz2 linux-stable-35c7ab421a13f8327e3fd627c6ebafb1c13b2e55.zip | |
drm/i915: reserve I915_CACHING_DISPLAY and document cache modes
Resolve the catch-22 of igt needing a stable number and patches first
needing testcases by reserving the interface number up-front.
v2: Improve the spelling a bit.
v3: More spelling fail spotted by Chris.
Requested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include/uapi/drm')
| -rw-r--r-- | include/uapi/drm/i915_drm.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index a1a7b6bd60d8..0bb3e5524382 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -768,8 +768,32 @@ struct drm_i915_gem_busy { __u32 busy; }; +/** + * I915_CACHING_NONE + * + * GPU access is not coherent with cpu caches. Default for machines without an + * LLC. + */ #define I915_CACHING_NONE 0 +/** + * I915_CACHING_CACHED + * + * GPU access is coherent with cpu caches and furthermore the data is cached in + * last-level caches shared between cpu cores and the gpu GT. Default on + * machines with HAS_LLC. + */ #define I915_CACHING_CACHED 1 +/** + * I915_CACHING_DISPLAY + * + * Special GPU caching mode which is coherent with the scanout engines. + * Transparently falls back to I915_CACHING_NONE on platforms where no special + * cache mode (like write-through or gfdt flushing) is available. The kernel + * automatically sets this mode when using a buffer as a scanout target. + * Userspace can manually set this mode to avoid a costly stall and clflush in + * the hotpath of drawing the first frame. + */ +#define I915_CACHING_DISPLAY 2 struct drm_i915_gem_caching { /** |