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| author | Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> | 2023-10-18 14:32:53 +0300 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-10-24 10:54:04 -0500 |
| commit | 74f0b5ffe172f913c56e4f5291678bad2a55b6b1 (patch) | |
| tree | c4154b8dc0a4be3b5d7791856965ecc405951d13 /include/uapi/linux | |
| parent | f00e8dbdedfb0dc2b5712d2170e7fcbe4eb93603 (diff) | |
| download | linux-stable-74f0b5ffe172f913c56e4f5291678bad2a55b6b1.tar.gz linux-stable-74f0b5ffe172f913c56e4f5291678bad2a55b6b1.tar.bz2 linux-stable-74f0b5ffe172f913c56e4f5291678bad2a55b6b1.zip | |
PCI/DPC: Use defines with DPC reason fields
Add new defines for DPC reason fields and use them instead of literals.
Link: https://lore.kernel.org/r/20231018113254.17616-7-ilpo.jarvinen@linux.intel.com
Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
[bhelgaas: shorten comments]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/uapi/linux')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 6c1bad2cb04a..0fd621505246 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1044,9 +1044,15 @@ #define PCI_EXP_DPC_STATUS 0x08 /* DPC Status */ #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 /* Trigger Reason */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_UNCOR 0x0000 /* Uncorrectable error */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_NFE 0x0002 /* Rcvd ERR_NONFATAL */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_FE 0x0004 /* Rcvd ERR_FATAL */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_IN_EXT 0x0006 /* Reason in Trig Reason Extension field */ #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 /* Interrupt Status */ #define PCI_EXP_DPC_RP_BUSY 0x0010 /* Root Port Busy */ #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 /* Trig Reason Extension */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_RP_PIO 0x0000 /* RP PIO error */ +#define PCI_EXP_DPC_STATUS_TRIGGER_RSN_SW_TRIGGER 0x0020 /* DPC SW Trigger bit */ #define PCI_EXP_DPC_RP_PIO_FEP 0x1f00 /* RP PIO First Err Ptr */ #define PCI_EXP_DPC_SOURCE_ID 0x0A /* DPC Source Identifier */ |