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authorGustavo Padovan <gustavo.padovan@collabora.co.uk>2015-04-01 13:02:05 -0300
committerInki Dae <inki.dae@samsung.com>2015-04-13 11:39:39 +0900
commit453b44a3f6f3f43f50387a9af27c5356c273e831 (patch)
tree403d076fa884eabc865d4540a822c9c357573d4b /include/video
parent1d8ac08d498d579aae36221a80b4b724b2f52f39 (diff)
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drm/exynos: fimd: fix alpha setting for XR24 pixel format
XR24 planes were not shown properly, so now set the right registers to correctly enable displaying these planes. It also moves the alpha register settings to fimd_win_set_pixfmt() to keep all pixel format stuff together. v2: remove leftover var alpha Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk> Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'include/video')
-rw-r--r--include/video/samsung_fimd.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index a20e4a3a8b15..513242827b07 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -289,6 +289,11 @@
#define VIDISD14C_ALPHA1_B_LIMIT 0xf
#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
+#define VIDW_ALPHA 0x021c
+#define VIDW_ALPHA_R(_x) ((_x) << 16)
+#define VIDW_ALPHA_G(_x) ((_x) << 8)
+#define VIDW_ALPHA_B(_x) ((_x) << 0)
+
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))