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authorLi, Zhen-Hua <zhen-hual@hp.com>2013-09-13 14:27:32 +0800
committerJoerg Roedel <joro@8bytes.org>2013-09-24 13:04:07 +0200
commit82aeef0bf03684b377678c00c05e613f30dca39c (patch)
tree7348799eca051013d1d6b51ae7e5f7c4b231057d /include
parent0b6e8569b7b767f9418f1b043aa5986015a33b21 (diff)
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x86/iommu: correct ICS register offset
According to Intel Vt-D specs, the offset of Invalidation complete status register should be 0x9C, not 0x98. See Intel's VT-d spec, Revision 1.3, Chapter 10.4, Page 98; Signed-off-by: Li, Zhen-Hua <zhen-hual@hp.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
Diffstat (limited to 'include')
-rw-r--r--include/linux/intel-iommu.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 78e2ada50cd5..d380c5e68008 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -55,7 +55,7 @@
#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
#define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
-#define DMAR_ICS_REG 0x98 /* Invalidation complete status register */
+#define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
#define OFFSET_STRIDE (9)