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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2016-09-07 15:43:22 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-09-12 20:01:43 +0100 |
| commit | 7c7289a40425d48bbfcaacc454a8caf5b47f63b0 (patch) | |
| tree | 5b7789114fb9ae509a231e6f0d9b460ec7652378 /include | |
| parent | 96579a4e56bdecfb4642cfb68eb85d079acb9d28 (diff) | |
| download | linux-stable-7c7289a40425d48bbfcaacc454a8caf5b47f63b0.tar.gz linux-stable-7c7289a40425d48bbfcaacc454a8caf5b47f63b0.tar.bz2 linux-stable-7c7289a40425d48bbfcaacc454a8caf5b47f63b0.zip | |
spi: pxa2xx: Default thresholds to PXA configuration
Most of the devices in the supported list have PXA configuration of FIFO. In
particularly Intel Medfield and Merrifield have bigger FIFO, than it's defined
for CE4100.
Split CE4100 in the similar way how it was done for Intel Quark, i.e. prefix
definitions by CE4100 and append necessary pieces of code to switch case
conditions.
We are on safe side since those bits are ignored on all LPSS IPs.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/pxa2xx_ssp.h | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h index 2a097d176ba9..2d6f0c39ed68 100644 --- a/include/linux/pxa2xx_ssp.h +++ b/include/linux/pxa2xx_ssp.h @@ -83,7 +83,6 @@ #define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */ #define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */ -#ifdef CONFIG_ARCH_PXA #define RX_THRESH_DFLT 8 #define TX_THRESH_DFLT 8 @@ -95,19 +94,16 @@ #define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */ #define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */ -#else - -#define RX_THRESH_DFLT 2 -#define TX_THRESH_DFLT 2 +#define RX_THRESH_CE4100_DFLT 2 +#define TX_THRESH_CE4100_DFLT 2 -#define SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */ -#define SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */ +#define CE4100_SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */ +#define CE4100_SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */ -#define SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */ -#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */ -#define SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */ -#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ -#endif +#define CE4100_SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */ +#define CE4100_SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */ +#define CE4100_SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */ +#define CE4100_SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */ /* QUARK_X1000 SSCR0 bit definition */ #define QUARK_X1000_SSCR0_DSS (0x1F) /* Data Size Select (mask) */ |