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| author | Olof Johansson <olof@lixom.net> | 2019-04-28 23:07:03 -0700 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2019-04-28 23:07:03 -0700 |
| commit | b94d3ff97e2ce2ce6d63f526ed53e299d0861e86 (patch) | |
| tree | 853eee00d069414220f77ca244cac2ee372e5d0f /include | |
| parent | 0065198e6779ad3abfada87fe118f03e1a0ba888 (diff) | |
| parent | c09f7471127e9debf3e814ffef4f4012c31a5a3d (diff) | |
| download | linux-stable-b94d3ff97e2ce2ce6d63f526ed53e299d0861e86.tar.gz linux-stable-b94d3ff97e2ce2ce6d63f526ed53e299d0861e86.tar.bz2 linux-stable-b94d3ff97e2ce2ce6d63f526ed53e299d0861e86.zip | |
Merge tag 'zynqmp-soc-for-v5.2' of https://github.com/Xilinx/linux-xlnx into arm/drivers
arm64: zynqmp: SoC changes for v5.2
- Add support for ZynqMP fpga manager
- Defer some probes which depends on firmware driver to be ready
- Debugfs fix
* tag 'zynqmp-soc-for-v5.2' of https://github.com/Xilinx/linux-xlnx:
fpga manager: Adding FPGA Manager support for Xilinx zynqmp
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
firmware: xilinx: Add fpga API's
drivers: Defer probe if firmware is not ready
firmware: xilinx: fix debugfs write handler
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/firmware/xlnx-zynqmp.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 642dab10f65d..1262ea6a1f4b 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -48,6 +48,14 @@ #define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U #define ZYNQMP_PM_CAPABILITY_POWER 0x8U +/* + * Firmware FPGA Manager flags + * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration + * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration + */ +#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U +#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0) + enum pm_api_id { PM_GET_API_VERSION = 1, PM_REQUEST_NODE = 13, @@ -56,6 +64,8 @@ enum pm_api_id { PM_RESET_ASSERT = 17, PM_RESET_GET_STATUS, PM_PM_INIT_FINALIZE = 21, + PM_FPGA_LOAD, + PM_FPGA_GET_STATUS, PM_GET_CHIPID = 24, PM_IOCTL = 34, PM_QUERY_DATA, @@ -258,6 +268,8 @@ struct zynqmp_pm_query_data { struct zynqmp_eemi_ops { int (*get_api_version)(u32 *version); int (*get_chipid)(u32 *idcode, u32 *version); + int (*fpga_load)(const u64 address, const u32 size, const u32 flags); + int (*fpga_get_status)(u32 *value); int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out); int (*clock_enable)(u32 clock_id); int (*clock_disable)(u32 clock_id); @@ -293,7 +305,7 @@ const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { - return NULL; + return ERR_PTR(-ENODEV); } #endif |