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authorJerome Brunet <jbrunet@baylibre.com>2019-05-12 22:57:43 +0200
committerJerome Brunet <jbrunet@baylibre.com>2019-05-20 12:05:46 +0200
commite63b063ecd248ad9f54a961ddf2a6d97da944456 (patch)
tree2732b16bb2fb492d303e077f460849d8ea26d0e4 /include
parenta188339ca5a396acc588e5851ed7e19f66b0ebd9 (diff)
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clk: meson: fix MPLL 50M binding id typo
MPLL_5OM (the capital letter o) should indeed be MPLL_50M (the number) Fix this before it gets used. Fixes: 25db146aa726 ("dt-bindings: clk: meson: add g12a periph clock controller bindings") Reported-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/g12a-clkc.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/g12a-clkc.h b/include/dt-bindings/clock/g12a-clkc.h
index 82c9e0c020b2..e10470ed7c4f 100644
--- a/include/dt-bindings/clock/g12a-clkc.h
+++ b/include/dt-bindings/clock/g12a-clkc.h
@@ -130,7 +130,7 @@
#define CLKID_MALI_1_SEL 172
#define CLKID_MALI_1 174
#define CLKID_MALI 175
-#define CLKID_MPLL_5OM 177
+#define CLKID_MPLL_50M 177
#define CLKID_CPU_CLK 187
#define CLKID_PCIE_PLL 201
#define CLKID_VDEC_1 204