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author | Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-12 18:39:43 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2022-08-12 18:39:43 -0700 |
commit | 69dac8e431af26173ca0a1ebc87054e01c585bcc (patch) | |
tree | a39774497b82ceb4fda0d5dad3e7dd56700ad312 /io_uring/rw.c | |
parent | 6c833c0581f1c15db2e0344da19360cba75a3351 (diff) | |
parent | 5cef38dd03f33ef206eb792df0fb3b200d762546 (diff) | |
download | linux-stable-69dac8e431af26173ca0a1ebc87054e01c585bcc.tar.gz linux-stable-69dac8e431af26173ca0a1ebc87054e01c585bcc.tar.bz2 linux-stable-69dac8e431af26173ca0a1ebc87054e01c585bcc.zip |
Merge tag 'riscv-for-linus-5.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt:
"There's still a handful of new features in here, but there are a lot
of fixes/cleanups as well:
- Support for the Zicbom extension for explicit cache-block
management, along with the necessary bits to make the non-standard
cache management ops on the Allwinner D1 function
- Support for the Zihintpause extension, which codifies a go-slow
instruction used for cpu_relax()
- Support for the Sstc extension for supervisor-mode timer/counter
management
- Many device tree fixes and cleanups, including a large set for the
Canaan device trees
- A handful of fixes and cleanups for the PMU driver"
* tag 'riscv-for-linus-5.20-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (43 commits)
dt-bindings: gpio: sifive: add gpio-line-names
wireguard: selftests: set CONFIG_NONPORTABLE on riscv32
RISC-V: KVM: Support sstc extension
RISC-V: Improve SBI definitions
RISC-V: Move counter info definition to sbi header file
RISC-V: Fix SBI PMU calls for RV32
RISC-V: Update user page mapping only once during start
RISC-V: Fix counter restart during overflow for RV32
RISC-V: Prefer sstc extension if available
RISC-V: Enable sstc extension parsing from DT
RISC-V: Add SSTC extension CSR details
riscv:uprobe fix SR_SPIE set/clear handling
dt-bindings: riscv: fix SiFive l2-cache's cache-sets
riscv: ensure cpu_ops_sbi is declared
RISC-V: cpu_ops_spinwait.c should include head.h
RISC-V: Declare cpu_ops_spinwait in <asm/cpu_ops.h>
riscv: dts: starfive: correct number of external interrupts
riscv: dts: sifive unmatched: Add PWM controlled LEDs
riscv/purgatory: Omit use of bin2c
riscv/purgatory: hard-code obj-y in Makefile
...
Diffstat (limited to 'io_uring/rw.c')
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