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| author | Milton Miller <miltonm@bga.com> | 2007-09-21 18:09:02 -0500 |
|---|---|---|
| committer | Sam Ravnborg <sam@neptun.(none)> | 2007-10-12 21:20:32 +0200 |
| commit | 0b35786d77ba4037f181982cc8ca20a7a3bf0fd2 (patch) | |
| tree | cfbbd6aea0e46ff3be725421b8dc6d7bae89d09c /scripts/mkmakefile | |
| parent | cf851aa75694bdcc27a5092b2e45de6dcdc1cfa8 (diff) | |
| download | linux-stable-0b35786d77ba4037f181982cc8ca20a7a3bf0fd2.tar.gz linux-stable-0b35786d77ba4037f181982cc8ca20a7a3bf0fd2.tar.bz2 linux-stable-0b35786d77ba4037f181982cc8ca20a7a3bf0fd2.zip | |
kbuild: call make once for all targets when O=.. is used
Change the invocations of make in the output directory Makefile and the
main Makefile for separate object trees to pass all goals to one $(MAKE)
via a new phony target "sub-make" and the existing target _all.
When compiling with separate object directories, a separate make is called
in the context of another directory (from the output directory the main
Makefile is called, the Makefile is then restarted with current directory
set to the object tree). Before this patch, when multiple make command
goals are specified, each target results in a separate make invocation.
With make -j, these invocations may run in parallel, resulting in multiple
commands running in the same directory clobbering each others results.
I did not try to address make -j for mixed dot-config and no-dot-config
targets. Because the order does matter, a solution was not obvious.
Perhaps a simple check for MAKEFLAGS having -j and refusing to run would
be appropriate.
Signed-off-by: Milton Miller <miltonm@bga.com>
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Diffstat (limited to 'scripts/mkmakefile')
| -rw-r--r-- | scripts/mkmakefile | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/scripts/mkmakefile b/scripts/mkmakefile index 7f9d544f9b6c..ee39facee152 100644 --- a/scripts/mkmakefile +++ b/scripts/mkmakefile @@ -26,11 +26,13 @@ MAKEFLAGS += --no-print-directory .PHONY: all \$(MAKECMDGOALS) +all := \$(filter-out all Makefile,\$(MAKECMDGOALS)) + all: - \$(MAKE) -C \$(KERNELSRC) O=\$(KERNELOUTPUT) + \$(MAKE) -C \$(KERNELSRC) O=\$(KERNELOUTPUT) \$(all) Makefile:; -\$(filter-out all Makefile,\$(MAKECMDGOALS)) %/: - \$(MAKE) -C \$(KERNELSRC) O=\$(KERNELOUTPUT) \$@ +\$(all) %/: all + @: EOF |