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-rw-r--r--arch/arm/kernel/head-nommu.S2
-rw-r--r--arch/arm/kernel/head.S4
-rw-r--r--arch/arm/mach-pxa/sleep.S2
-rw-r--r--arch/arm/mach-s3c2410/sleep.S2
-rw-r--r--arch/arm/mach-sa1100/sleep.S2
-rw-r--r--arch/arm/nwfpe/entry26.S2
-rw-r--r--include/asm-arm/assembler.h7
7 files changed, 7 insertions, 14 deletions
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index adf62e5eaad7..2af7e44218af 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -39,7 +39,7 @@
__INIT
.type stext, %function
ENTRY(stext)
- msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
+ msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
@ and irqs disabled
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type @ r5=procinfo r9=cpuid
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 04f7344e356a..330b9476c398 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -71,7 +71,7 @@
__INIT
.type stext, %function
ENTRY(stext)
- msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
+ msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
@ and irqs disabled
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type @ r5=procinfo r9=cpuid
@@ -104,7 +104,7 @@ ENTRY(secondary_startup)
* the processor type - there is no need to check the machine type
* as it has already been validated by the primary processor.
*/
- msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
+ msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
mrc p15, 0, r9, c0, c0 @ get processor id
bl __lookup_processor_type
movs r10, r5 @ invalid processor?
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index c9862688ff3d..0650bed3b96e 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -189,7 +189,7 @@ ENTRY(pxa_cpu_suspend)
.data
.align 5
ENTRY(pxa_cpu_resume)
- mov r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC @ set SVC, irqs off
+ mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
msr cpsr_c, r0
ldr r0, sleep_save_sp @ stack phys addr
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 5f6761ed96b2..dc27167f4d59 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -128,7 +128,7 @@ s3c2410_sleep_save_phys:
*/
ENTRY(s3c2410_cpu_resume)
- mov r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC
+ mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
msr cpsr_c, r0
@@ load UART to allow us to print the two characters for
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 2fa1e289d177..5a84062f92af 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -177,7 +177,7 @@ sa1110_sdram_controller_fix:
.data
.align 5
ENTRY(sa1100_cpu_resume)
- mov r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
+ mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
msr cpsr_c, r0 @ set SVC, irqs off
ldr r0, sleep_save_sp @ stack phys addr
diff --git a/arch/arm/nwfpe/entry26.S b/arch/arm/nwfpe/entry26.S
index 51940a96d6a6..3e6fb5d21d64 100644
--- a/arch/arm/nwfpe/entry26.S
+++ b/arch/arm/nwfpe/entry26.S
@@ -26,7 +26,7 @@
It is called from the kernel with code similar to this:
mov fp, #0
- teqp pc, #PSR_I_BIT | MODE_SVC
+ teqp pc, #PSR_I_BIT | SVC_MODE
ldr r4, .LC2
ldr pc, [r4] @ Call FP module USR entry point
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index b97cb3e1ba72..fce832820825 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -55,13 +55,6 @@
#define PLD(code...)
#endif
-#define MODE_USR USR_MODE
-#define MODE_FIQ FIQ_MODE
-#define MODE_IRQ IRQ_MODE
-#define MODE_SVC SVC_MODE
-
-#define DEFAULT_FIQ MODE_FIQ
-
/*
* Enable and disable interrupts
*/