diff options
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 40 | ||||
| -rw-r--r-- | drivers/clk/meson/meson8b.h | 13 |
2 files changed, 48 insertions, 5 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 8f29d26ed726..21bc29455f0d 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -118,6 +118,35 @@ static struct clk_regmap meson8b_fixed_pll = { }, }; +static struct clk_fixed_factor hdmi_pll_dco_in = { + .mult = 2, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "hdmi_pll_dco_in", + .ops = &clk_fixed_factor_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + .index = -1, + }, + .num_parents = 1, + }, +}; + +/* + * Taken from the vendor driver for the 2970/2975MHz (both only differ in the + * FRAC part in HHI_VID_PLL_CNTL2) where these values are identical for Meson8, + * Meson8b and Meson8m2. This doubles the input (or output - it's not clear + * which one but the result is the same) clock. The vendor driver additionally + * has the following comment about: "optimise HPLL VCO 2.97GHz performance". + */ +static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = { + { .reg = HHI_VID_PLL_CNTL2, .def = 0x69c84000 }, + { .reg = HHI_VID_PLL_CNTL3, .def = 0x8a46c023 }, + { .reg = HHI_VID_PLL_CNTL4, .def = 0x4123b100 }, + { .reg = HHI_VID_PLL_CNTL5, .def = 0x00012385 }, + { .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 }, +}; + static const struct pll_params_table hdmi_pll_params_table[] = { PLL_PARAMS(40, 1), PLL_PARAMS(42, 1), @@ -172,15 +201,15 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { .width = 1, }, .table = hdmi_pll_params_table, + .init_regs = meson8b_hdmi_pll_init_regs, + .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs), }, .hw.init = &(struct clk_init_data){ /* sometimes also called "HPLL" or "HPLL PLL" */ .name = "hdmi_pll_dco", .ops = &meson_clk_pll_ro_ops, - .parent_data = &(const struct clk_parent_data) { - .fw_name = "xtal", - .name = "xtal", - .index = -1, + .parent_hws = (const struct clk_hw *[]) { + &hdmi_pll_dco_in.hw }, .num_parents = 1, }, @@ -2945,6 +2974,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, [CLKID_CTS_I958] = &meson8b_cts_i958.hw, [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, + [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -3163,6 +3193,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, [CLKID_CTS_I958] = &meson8b_cts_i958.hw, [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, + [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, @@ -3383,6 +3414,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = { [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, [CLKID_CTS_I958] = &meson8b_cts_i958.hw, [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, + [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, [CLK_NR_CLKS] = NULL, }, .num = CLK_NR_CLKS, diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h index b90c21bbd907..ce62ed47cbfc 100644 --- a/drivers/clk/meson/meson8b.h +++ b/drivers/clk/meson/meson8b.h @@ -51,6 +51,16 @@ #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ #define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ +#define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ +#define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */ +#define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ +#define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ +#define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */ +#define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */ +#define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */ +#define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */ +#define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */ +#define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */ /* * MPLL register offeset taken from the S905 datasheet. Vendor kernel source @@ -173,8 +183,9 @@ #define CLKID_VCLK_EN 214 #define CLKID_VCLK2_EN 215 #define CLKID_VID_PLL_LVDS_EN 216 +#define CLKID_HDMI_PLL_DCO_IN 217 -#define CLK_NR_CLKS 217 +#define CLK_NR_CLKS 218 /* * include the CLKID and RESETID that have |