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-rw-r--r--arch/powerpc/perf/core-book3s.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 5d502bf374ea..517a1350b09c 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -75,6 +75,7 @@ static unsigned int freeze_events_kernel = MMCR0_FCS;
#define MMCR0_FCHV 0
#define MMCR0_PMCjCE MMCR0_PMCnCE
+#define MMCR0_FC56 0
#define MMCR0_PMAO 0
#define SPRN_MMCRA SPRN_MMCR2
@@ -870,11 +871,11 @@ static void power_pmu_disable(struct pmu *pmu)
}
/*
- * Set the 'freeze counters' bit, clear PMAO.
+ * Set the 'freeze counters' bit, clear PMAO/FC56.
*/
val = mfspr(SPRN_MMCR0);
val |= MMCR0_FC;
- val &= ~MMCR0_PMAO;
+ val &= ~(MMCR0_PMAO | MMCR0_FC56);
/*
* The barrier is to make sure the mtspr has been