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path: root/drivers/gpu/drm/i915/i915_drv.h
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Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h22
1 files changed, 0 insertions, 22 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 821ba26438fb..9962da202456 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -968,23 +968,6 @@ struct intel_rps_ei {
u32 media_c0;
};
-struct intel_rps_bdw_cal {
- u32 it_threshold_pct; /* interrupt, in percentage */
- u32 eval_interval; /* evaluation interval, in us */
- u32 last_ts;
- u32 last_c0;
- bool is_up;
-};
-
-struct intel_rps_bdw_turbo {
- struct intel_rps_bdw_cal up;
- struct intel_rps_bdw_cal down;
- struct timer_list flip_timer;
- u32 timeout;
- atomic_t flip_received;
- struct work_struct work_max_freq;
-};
-
struct intel_gen6_power_mgmt {
/* work and pm_iir are protected by dev_priv->irq_lock */
struct work_struct work;
@@ -1018,9 +1001,6 @@ struct intel_gen6_power_mgmt {
bool enabled;
struct delayed_work delayed_resume_work;
- bool is_bdw_sw_turbo; /* Switch of BDW software turbo */
- struct intel_rps_bdw_turbo sw_turbo; /* Calculate RP interrupt timing */
-
/* manual wa residency calculations */
struct intel_rps_ei up_ei, down_ei;
@@ -2857,8 +2837,6 @@ extern void intel_disable_fbc(struct drm_device *dev);
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
extern void intel_init_pch_refclk(struct drm_device *dev);
extern void gen6_set_rps(struct drm_device *dev, u8 val);
-extern void bdw_software_turbo(struct drm_device *dev);
-extern void gen8_flip_interrupt(struct drm_device *dev);
extern void valleyview_set_rps(struct drm_device *dev, u8 val);
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
bool enable);