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path: root/drivers/gpu/drm/rcar-du/rcar_du_group.c
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Diffstat (limited to 'drivers/gpu/drm/rcar-du/rcar_du_group.c')
-rw-r--r--drivers/gpu/drm/rcar-du/rcar_du_group.c94
1 files changed, 60 insertions, 34 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index d539cb290a35..d85f0a1c1581 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -1,14 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
* rcar_du_group.c -- R-Car Display Unit Channels Pair
*
* Copyright (C) 2013-2015 Renesas Electronics Corporation
*
* Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
*/
/*
@@ -60,8 +56,6 @@ static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
{
struct rcar_du_device *rcdu = rgrp->dev;
- unsigned int possible_crtcs =
- rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
u32 defr8 = DEFR8_CODE;
if (rcdu->info->gen < 3) {
@@ -73,26 +67,71 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
* DU instances that support it.
*/
if (rgrp->index == 0) {
- if (possible_crtcs > 1)
- defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
+ defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
if (rgrp->dev->vspd1_sink == 2)
defr8 |= DEFR8_VSCS;
}
} else {
/*
- * On Gen3 VSPD routing can't be configured, but DPAD routing
- * needs to be set despite having a single option available.
+ * On Gen3 VSPD routing can't be configured, and DPAD routing
+ * is set in the group corresponding to the DPAD output (no Gen3
+ * SoC has multiple DPAD sources belonging to separate groups).
*/
- unsigned int rgb_crtc = ffs(possible_crtcs) - 1;
- struct rcar_du_crtc *crtc = &rcdu->crtcs[rgb_crtc];
-
- if (crtc->index / 2 == rgrp->index)
- defr8 |= DEFR8_DRGBS_DU(crtc->index);
+ if (rgrp->index == rcdu->dpad0_source / 2)
+ defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
}
rcar_du_group_write(rgrp, DEFR8, defr8);
}
+static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp)
+{
+ struct rcar_du_device *rcdu = rgrp->dev;
+ struct rcar_du_crtc *rcrtc;
+ unsigned int num_crtcs = 0;
+ unsigned int i;
+ u32 didsr;
+
+ /*
+ * Configure input dot clock routing with a hardcoded configuration. If
+ * the DU channel can use the LVDS encoder output clock as the dot
+ * clock, do so. Otherwise route DU_DOTCLKINn signal to DUn.
+ *
+ * Each channel can then select between the dot clock configured here
+ * and the clock provided by the CPG through the ESCR register.
+ */
+ if (rcdu->info->gen < 3 && rgrp->index == 0) {
+ /*
+ * On Gen2 a single register in the first group controls dot
+ * clock selection for all channels.
+ */
+ rcrtc = rcdu->crtcs;
+ num_crtcs = rcdu->num_crtcs;
+ } else if (rcdu->info->gen == 3 && rgrp->num_crtcs > 1) {
+ /*
+ * On Gen3 dot clocks are setup through per-group registers,
+ * only available when the group has two channels.
+ */
+ rcrtc = &rcdu->crtcs[rgrp->index * 2];
+ num_crtcs = rgrp->num_crtcs;
+ }
+
+ if (!num_crtcs)
+ return;
+
+ didsr = DIDSR_CODE;
+ for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
+ if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
+ didsr |= DIDSR_LCDS_LVDS0(i)
+ | DIDSR_PDCS_CLK(i, 0);
+ else
+ didsr |= DIDSR_LCDS_DCLKIN(i)
+ | DIDSR_PDCS_CLK(i, 0);
+ }
+
+ rcar_du_group_write(rgrp, DIDSR, didsr);
+}
+
static void rcar_du_group_setup(struct rcar_du_group *rgrp)
{
struct rcar_du_device *rcdu = rgrp->dev;
@@ -110,21 +149,7 @@ static void rcar_du_group_setup(struct rcar_du_group *rgrp)
if (rcar_du_has(rgrp->dev, RCAR_DU_FEATURE_EXT_CTRL_REGS)) {
rcar_du_group_setup_defr8(rgrp);
-
- /*
- * Configure input dot clock routing. We currently hardcode the
- * configuration to routing DOTCLKINn to DUn. Register fields
- * depend on the DU generation, but the resulting value is 0 in
- * all cases.
- *
- * On Gen2 a single register in the first group controls dot
- * clock selection for all channels, while on Gen3 dot clocks
- * are setup through per-group registers, only available when
- * the group has two channels.
- */
- if ((rcdu->info->gen < 3 && rgrp->index == 0) ||
- (rcdu->info->gen == 3 && rgrp->num_crtcs > 1))
- rcar_du_group_write(rgrp, DIDSR, DIDSR_CODE);
+ rcar_du_group_setup_didsr(rgrp);
}
if (rcdu->info->gen >= 3)
@@ -177,9 +202,10 @@ void rcar_du_group_put(struct rcar_du_group *rgrp)
static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
{
- rcar_du_group_write(rgrp, DSYSR,
- (rcar_du_group_read(rgrp, DSYSR) & ~(DSYSR_DRES | DSYSR_DEN)) |
- (start ? DSYSR_DEN : DSYSR_DRES));
+ struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2];
+
+ rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
+ start ? DSYSR_DEN : DSYSR_DRES);
}
void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)