diff options
Diffstat (limited to 'drivers')
22 files changed, 2148 insertions, 2387 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 2eac737b73a3..7cacf89f8838 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -324,6 +324,7 @@ source "drivers/pinctrl/ti/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" +source "drivers/pinctrl/zte/Kconfig" config PINCTRL_XWAY bool diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index bdf7ba9f676f..a054364c1e2f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -59,3 +59,4 @@ obj-y += ti/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-$(CONFIG_PINCTRL_MTK) += mediatek/ +obj-$(CONFIG_PINCTRL_ZX) += zte/ diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 1653cbda6a82..80d2314bc8a7 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -170,7 +170,7 @@ const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin) const struct pin_desc *desc; desc = pin_desc_get(pctldev, pin); - if (desc == NULL) { + if (!desc) { dev_err(pctldev->dev, "failed to get pin(%d) name\n", pin); return NULL; @@ -214,7 +214,7 @@ static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev, pindesc = radix_tree_lookup(&pctldev->pin_desc_tree, pins[i].number); - if (pindesc != NULL) { + if (pindesc) { radix_tree_delete(&pctldev->pin_desc_tree, pins[i].number); if (pindesc->dynamic_name) @@ -230,7 +230,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, struct pin_desc *pindesc; pindesc = pin_desc_get(pctldev, pin->number); - if (pindesc != NULL) { + if (pindesc) { dev_err(pctldev->dev, "pin %d already registered\n", pin->number); return -EINVAL; @@ -248,7 +248,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, pindesc->name = pin->name; } else { pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", pin->number); - if (pindesc->name == NULL) { + if (!pindesc->name) { kfree(pindesc); return -ENOMEM; } @@ -402,7 +402,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio, struct pinctrl_gpio_range *range; range = pinctrl_match_gpio_range(pctldev, gpio); - if (range != NULL) { + if (range) { *outdev = pctldev; *outrange = range; mutex_unlock(&pinctrldev_list_mutex); @@ -947,7 +947,7 @@ static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev, else setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); - if (setting->pctldev == NULL) { + if (!setting->pctldev) { kfree(setting); /* Do not defer probing of hogs (circular loop) */ if (!strcmp(map->ctrl_dev_name, map->dev_name)) @@ -1038,6 +1038,16 @@ static struct pinctrl *create_pinctrl(struct device *dev, /* Map must be for this device */ if (strcmp(map->dev_name, devname)) continue; + /* + * If pctldev is not null, we are claiming hog for it, + * that means, setting that is served by pctldev by itself. + * + * Thus we must skip map that is for this device but is served + * by other device. + */ + if (pctldev && + strcmp(dev_name(pctldev->dev), map->ctrl_dev_name)) + continue; ret = add_setting(p, pctldev, map); /* @@ -1094,7 +1104,7 @@ struct pinctrl *pinctrl_get(struct device *dev) * return another pointer to it. */ p = find_pinctrl(dev); - if (p != NULL) { + if (p) { dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n"); kref_get(&p->users); return p; @@ -1565,7 +1575,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what) pin = pctldev->desc->pins[i].number; desc = pin_desc_get(pctldev, pin); /* Pin space may be sparse */ - if (desc == NULL) + if (!desc) continue; seq_printf(s, "pin %d (%s) ", pin, desc->name); @@ -1732,7 +1742,7 @@ static int pinctrl_maps_show(struct seq_file *s, void *what) break; } - seq_printf(s, "\n"); + seq_putc(s, '\n'); } mutex_unlock(&pinctrl_maps_mutex); @@ -2145,7 +2155,7 @@ void pinctrl_unregister(struct pinctrl_dev *pctldev) { struct pinctrl_gpio_range *range, *n; - if (pctldev == NULL) + if (!pctldev) return; mutex_lock(&pctldev->mutex); diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index cae05e76c111..0b266b2aecd4 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -2,7 +2,7 @@ config PINCTRL_IMX bool select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select PINCONF + select GENERIC_PINCONF select REGMAP config PINCTRL_IMX1_CORE diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 74bd90dfd7b1..72aca758f4c6 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -27,6 +27,7 @@ #include <linux/regmap.h> #include "../core.h" +#include "../pinconf.h" #include "../pinmux.h" #include "pinctrl-imx.h" @@ -196,14 +197,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~(0x7 << 20); - reg |= (pin->mux_mode << 20); + reg &= ~info->mux_mask; + reg |= (pin->mux_mode << info->mux_shift); writel(reg, ipctl->base + pin_reg->mux_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->mux_reg, reg); } else { writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->mux_reg, pin->mux_mode); } - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, pin->mux_mode); /* * If the select input value begins with 0xff, it's a quirky @@ -287,7 +290,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, mux_pin: reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~(0x7 << 20); + reg &= ~info->mux_mask; reg |= imx_pin->config; writel(reg, ipctl->base + pin_reg->mux_reg); @@ -359,6 +362,62 @@ static const struct pinmux_ops imx_pmx_ops = { .gpio_set_direction = imx_pmx_gpio_set_direction, }; +/* decode generic config into raw register values */ +static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, + unsigned long *configs, + unsigned int num_configs) +{ + struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_cfg_params_decode *decode; + enum pin_config_param param; + u32 raw_config = 0; + u32 param_val; + int i, j; + + WARN_ON(num_configs > info->num_decodes); + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + param_val = pinconf_to_config_argument(configs[i]); + decode = info->decodes; + for (j = 0; j < info->num_decodes; j++) { + if (param == decode->param) { + if (decode->invert) + param_val = !param_val; + raw_config |= (param_val << decode->shift) + & decode->mask; + break; + } + decode++; + } + } + + if (info->fixup) + info->fixup(configs, num_configs, &raw_config); + + return raw_config; +} + +static u32 imx_pinconf_parse_generic_config(struct device_node *np, + struct imx_pinctrl *ipctl) +{ + struct imx_pinctrl_soc_info *info = ipctl->info; + struct pinctrl_dev *pctl = ipctl->pctl; + unsigned int num_configs; + unsigned long *configs; + int ret; + + if (!info->generic_pinconf) + return 0; + + ret = pinconf_generic_parse_dt_config(np, pctl, &configs, + &num_configs); + if (ret) + return 0; + + return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); +} + static int imx_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned long *config) { @@ -375,7 +434,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, *config = readl(ipctl->base + pin_reg->conf_reg); if (info->flags & SHARE_MUX_CONF_REG) - *config &= 0xffff; + *config &= ~info->mux_mask; return 0; } @@ -402,14 +461,16 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; reg = readl(ipctl->base + pin_reg->conf_reg); - reg &= ~0xffff; + reg &= info->mux_mask; reg |= configs[i]; writel(reg, ipctl->base + pin_reg->conf_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->conf_reg, reg); } else { writel(configs[i], ipctl->base + pin_reg->conf_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", + pin_reg->conf_reg, configs[i]); } - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", - pin_reg->conf_reg, configs[i]); } /* for each config */ return 0; @@ -475,9 +536,10 @@ static const struct pinconf_ops imx_pinconf_ops = { static int imx_pinctrl_parse_groups(struct device_node *np, struct group_desc *grp, - struct imx_pinctrl_soc_info *info, + struct imx_pinctrl *ipctl, u32 index) { + struct imx_pinctrl_soc_info *info = ipctl->info; int size, pin_size; const __be32 *list; int i; @@ -489,25 +551,44 @@ static int imx_pinctrl_parse_groups(struct device_node *np, pin_size = SHARE_FSL_PIN_SIZE; else pin_size = FSL_PIN_SIZE; + + if (info->generic_pinconf) + pin_size -= 4; + /* Initialise group */ grp->name = np->name; /* * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, * do sanity check and calculate pins number + * + * First try legacy 'fsl,pins' property, then fall back to the + * generic 'pins'. + * + * Note: for generic 'pins' case, there's no CONFIG part in + * the binding format. */ list = of_get_property(np, "fsl,pins", &size); if (!list) { - dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); - return -EINVAL; + list = of_get_property(np, "pins", &size); + if (!list) { + dev_err(info->dev, + "no fsl,pins and pins property in node %s\n", + np->full_name); + return -EINVAL; + } } /* we do not check return since it's safe node passed down */ if (!size || size % pin_size) { - dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); + dev_err(info->dev, "Invalid fsl,pins or pins property in node %s\n", + np->full_name); return -EINVAL; } + /* first try to parse the generic pin config */ + config = imx_pinconf_parse_generic_config(np, ipctl); + grp->num_pins = size / pin_size; grp->data = devm_kzalloc(info->dev, grp->num_pins * sizeof(struct imx_pin), GFP_KERNEL); @@ -544,11 +625,18 @@ static int imx_pinctrl_parse_groups(struct device_node *np, pin->mux_mode = be32_to_cpu(*list++); pin->input_val = be32_to_cpu(*list++); - /* SION bit is in mux register */ - config = be32_to_cpu(*list++); - if (config & IMX_PAD_SION) - pin->mux_mode |= IOMUXC_CONFIG_SION; - pin->config = config & ~IMX_PAD_SION; + if (info->generic_pinconf) { + /* generic pin config decoded */ + pin->config = config; + } else { + /* legacy pin config read from devicetree */ + config = be32_to_cpu(*list++); + + /* SION bit is in mux register */ + if (config & IMX_PAD_SION) + pin->mux_mode |= IOMUXC_CONFIG_SION; + pin->config = config & ~IMX_PAD_SION; + } dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, pin->mux_mode, pin->config); @@ -581,9 +669,10 @@ static int imx_pinctrl_parse_functions(struct device_node *np, dev_err(info->dev, "no groups defined in %s\n", np->full_name); return -EINVAL; } - func->group_names = devm_kzalloc(info->dev, - func->num_group_names * + func->group_names = devm_kcalloc(info->dev, func->num_group_names, sizeof(char *), GFP_KERNEL); + if (!func->group_names) + return -ENOMEM; for_each_child_of_node(np, child) { func->group_names[i] = child->name; @@ -598,7 +687,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, info->group_index++, grp); mutex_unlock(&info->mutex); - imx_pinctrl_parse_groups(child, grp, info, i++); + imx_pinctrl_parse_groups(child, grp, ipctl, i++); } return 0; @@ -769,6 +858,10 @@ int imx_pinctrl_probe(struct platform_device *pdev, imx_pinctrl_desc->confops = &imx_pinconf_ops; imx_pinctrl_desc->owner = THIS_MODULE; + /* for generic pinconf */ + imx_pinctrl_desc->custom_params = info->custom_params; + imx_pinctrl_desc->num_custom_params = info->num_custom_params; + mutex_init(&info->mutex); ipctl->info = info; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index ff2d3e56b7c5..880bba7fd1ab 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -15,6 +15,8 @@ #ifndef __DRIVERS_PINCTRL_IMX_H #define __DRIVERS_PINCTRL_IMX_H +#include <linux/pinctrl/pinconf-generic.h> + struct platform_device; /** @@ -44,6 +46,14 @@ struct imx_pin_reg { s16 conf_reg; }; +/* decode a generic config into raw register value */ +struct imx_cfg_params_decode { + enum pin_config_param param; + u32 mask; + u8 shift; + bool invert; +}; + struct imx_pinctrl_soc_info { struct device *dev; const struct pinctrl_pin_desc *pins; @@ -53,8 +63,27 @@ struct imx_pinctrl_soc_info { unsigned int flags; const char *gpr_compatible; struct mutex mutex; + + /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */ + unsigned int mux_mask; + u8 mux_shift; + + /* generic pinconf */ + bool generic_pinconf; + const struct pinconf_generic_params *custom_params; + unsigned int num_custom_params; + struct imx_cfg_params_decode *decodes; + unsigned int num_decodes; + void (*fixup)(unsigned long *configs, unsigned int num_configs, + u32 *raw_config); }; +#define IMX_CFG_PARAMS_DECODE(p, m, o) \ + { .param = p, .mask = m, .shift = o, .invert = false, } + +#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ + { .param = p, .mask = m, .shift = o, .invert = true, } + #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2 diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index 2b1e198e3092..3bd85564d1e4 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -299,6 +299,8 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_info = { .pins = vf610_pinctrl_pads, .npins = ARRAY_SIZE(vf610_pinctrl_pads), .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID, + .mux_mask = 0x700000, + .mux_shift = 20, }; static const struct of_device_id vf610_pinctrl_of_match[] = { diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 80fe3b48796c..fac9866311f3 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -11,18 +11,11 @@ config PINCTRL_MTK # For ARMv7 SoCs config PINCTRL_MT2701 bool "Mediatek MT2701 pin control" - depends on MACH_MT2701 || COMPILE_TEST + depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST depends on OF default MACH_MT2701 select PINCTRL_MTK -config PINCTRL_MT7623 - bool "Mediatek MT7623 pin control" - depends on MACH_MT7623 || COMPILE_TEST - depends on OF - default MACH_MT7623 - select PINCTRL_MTK_COMMON - config PINCTRL_MT8135 bool "Mediatek MT8135 pin control" depends on MACH_MT8135 || COMPILE_TEST diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 3e3390a14716..e59c613d4ddd 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -3,7 +3,6 @@ obj-y += pinctrl-mtk-common.o # SoC Drivers obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o -obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index 8d802fa7decd..f86f3b379607 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -565,6 +565,7 @@ static int mt2701_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id mt2701_pctrl_match[] = { { .compatible = "mediatek,mt2701-pinctrl", }, + { .compatible = "mediatek,mt7623-pinctrl", }, {} }; MODULE_DEVICE_TABLE(of, mt2701_pctrl_match); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c deleted file mode 100644 index fa28dd6b871b..000000000000 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright (c) 2016 John Crispin <john@phrozen.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <dt-bindings/pinctrl/mt65xx.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/platform_device.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/regmap.h> - -#include "pinctrl-mtk-common.h" -#include "pinctrl-mtk-mt7623.h" - -static const struct mtk_drv_group_desc mt7623_drv_grp[] = { - /* 0E4E8SR 4/8/12/16 */ - MTK_DRV_GRP(4, 16, 1, 2, 4), - /* 0E2E4SR 2/4/6/8 */ - MTK_DRV_GRP(2, 8, 1, 2, 2), - /* E8E4E2 2/4/6/8/10/12/14/16 */ - MTK_DRV_GRP(2, 16, 0, 2, 2) -}; - -#define DRV_SEL0 0xf50 -#define DRV_SEL1 0xf60 -#define DRV_SEL2 0xf70 -#define DRV_SEL3 0xf80 -#define DRV_SEL4 0xf90 -#define DRV_SEL5 0xfa0 -#define DRV_SEL6 0xfb0 -#define DRV_SEL7 0xfe0 -#define DRV_SEL8 0xfd0 -#define DRV_SEL9 0xff0 -#define DRV_SEL10 0xf00 - -#define MSDC0_CTRL0 0xcc0 -#define MSDC0_CTRL1 0xcd0 -#define MSDC0_CTRL2 0xce0 -#define MSDC0_CTRL3 0xcf0 -#define MSDC0_CTRL4 0xd00 -#define MSDC0_CTRL5 0xd10 -#define MSDC0_CTRL6 0xd20 -#define MSDC1_CTRL0 0xd30 -#define MSDC1_CTRL1 0xd40 -#define MSDC1_CTRL2 0xd50 -#define MSDC1_CTRL3 0xd60 -#define MSDC1_CTRL4 0xd70 -#define MSDC1_CTRL5 0xd80 -#define MSDC1_CTRL6 0xd90 - -#define IES_EN0 0xb20 -#define IES_EN1 0xb30 -#define IES_EN2 0xb40 - -#define SMT_EN0 0xb50 -#define SMT_EN1 0xb60 -#define SMT_EN2 0xb70 - -static const struct mtk_pin_drv_grp mt7623_pin_drv[] = { - MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1), - MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1), - MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1), - MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1), - MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1), - MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1), - MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1), - MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0), - MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0), - MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0), - MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0), - MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0), - MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0), - MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0), - MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0), - MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0), - MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1), - MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1), - MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1), - MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1), - MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0), - MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0), - MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0), - MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0), - MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0), - MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0), - MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0), - MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0), - MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0), - MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1), - MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1), - MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1), - MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1), - MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1), - MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1), - MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1), - MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1), - MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1), - MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1), - MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1), - MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0), - MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0), - MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0), - MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0), - MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0), - MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0), - MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1), -}; - -static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = { - MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2), - MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6), - MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14), - MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14), - MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6), - MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2), - MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2), - MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14), - MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6), - MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2), -}; - -static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd, - ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0); -} - -static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = { - MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0), - MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1), - MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2), - MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3), - MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5), - MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6), - MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7), - MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8), - MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9), - MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10), - MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11), - MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12), - MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14), - MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0), - MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1), - MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2), - MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12), - MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3), - MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2), - MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4), - MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7), - MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12), - MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1), - MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2), - MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3), - MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6), - MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7), - MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4), - MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12), - MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12), - MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13), -}; - -static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = { - MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0), - MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1), - MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2), - MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3), - MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5), - MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6), - MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7), - MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8), - MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9), - MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10), - MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11), - MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12), - MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14), - MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0), - MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1), - MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2), - MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12), - MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3), - MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2), - MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11), - MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3), - MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7), - MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11), - MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15), - MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11), - MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7), - MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3), - MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11), - MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15), - MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11), - MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7), - MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3), - MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7), - MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12), - MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1), - MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2), - MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3), - MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6), - MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7), - MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3), - MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12), - MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12), - MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13), -}; - -static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set, - ARRAY_SIZE(mt7623_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set, - ARRAY_SIZE(mt7623_smt_set), pin, align, value); - return -EINVAL; -} - -static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = { - .pins = mtk_pins_mt7623, - .npins = ARRAY_SIZE(mtk_pins_mt7623), - .grp_desc = mt7623_drv_grp, - .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp), - .pin_drv_grp = mt7623_pin_drv, - .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv), - .spec_pull_set = mt7623_spec_pull_set, - .spec_ies_smt_set = mt7623_ies_smt_set, - .dir_offset = 0x0000, - .pullen_offset = 0x0150, - .pullsel_offset = 0x0280, - .dout_offset = 0x0500, - .din_offset = 0x0630, - .pinmux_offset = 0x0760, - .type1_start = 280, - .type1_end = 280, - .port_shf = 4, - .port_mask = 0x1f, - .port_align = 4, - .eint_offsets = { - .name = "mt7623_eint", - .stat = 0x000, - .ack = 0x040, - .mask = 0x080, - .mask_set = 0x0c0, - .mask_clr = 0x100, - .sens = 0x140, - .sens_set = 0x180, - .sens_clr = 0x1c0, - .soft = 0x200, - .soft_set = 0x240, - .soft_clr = 0x280, - .pol = 0x300, - .pol_set = 0x340, - .pol_clr = 0x380, - .dom_en = 0x400, - .dbnc_ctrl = 0x500, - .dbnc_set = 0x600, - .dbnc_clr = 0x700, - .port_mask = 6, - .ports = 6, - }, - .ap_num = 169, - .db_cnt = 16, -}; - -static int mt7623_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL); -} - -static const struct of_device_id mt7623_pctrl_match[] = { - { .compatible = "mediatek,mt7623-pinctrl", }, - {} -}; -MODULE_DEVICE_TABLE(of, mt7623_pctrl_match); - -static struct platform_driver mtk_pinctrl_driver = { - .probe = mt7623_pinctrl_probe, - .driver = { - .name = "mediatek-mt7623-pinctrl", - .of_match_table = mt7623_pctrl_match, - }, -}; - -static int __init mtk_pinctrl_init(void) -{ - return platform_driver_register(&mtk_pinctrl_driver); -} - -arch_initcall(mtk_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h deleted file mode 100644 index e06cfc40da0f..000000000000 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h +++ /dev/null @@ -1,1936 +0,0 @@ -/* - * Copyright (c) 2016 John Crispin <john@phrozen.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __PINCTRL_MTK_MT7623_H -#define __PINCTRL_MTK_MT7623_H - -#include <linux/pinctrl/pinctrl.h> -#include "pinctrl-mtk-common.h" - -static const struct mtk_desc_pin mtk_pins_mt7623[] = { - MTK_PIN( - PINCTRL_PIN(0, "PWRAP_SPI0_MI"), - "J20", "mt7623", - MTK_EINT_FUNCTION(0, 148), - MTK_FUNCTION(0, "GPIO0"), - MTK_FUNCTION(1, "PWRAP_SPIDO"), - MTK_FUNCTION(2, "PWRAP_SPIDI") - ), - MTK_PIN( - PINCTRL_PIN(1, "PWRAP_SPI0_MO"), - "D10", "mt7623", - MTK_EINT_FUNCTION(0, 149), - MTK_FUNCTION(0, "GPIO1"), - MTK_FUNCTION(1, "PWRAP_SPIDI"), - MTK_FUNCTION(2, "PWRAP_SPIDO") - ), - MTK_PIN( - PINCTRL_PIN(2, "PWRAP_INT"), - "E11", "mt7623", - MTK_EINT_FUNCTION(0, 150), - MTK_FUNCTION(0, "GPIO2"), - MTK_FUNCTION(1, "PWRAP_INT") - ), - MTK_PIN( - PINCTRL_PIN(3, "PWRAP_SPI0_CK"), - "H12", "mt7623", - MTK_EINT_FUNCTION(0, 151), - MTK_FUNCTION(0, "GPIO3"), - MTK_FUNCTION(1, "PWRAP_SPICK_I") - ), - MTK_PIN( - PINCTRL_PIN(4, "PWRAP_SPI0_CSN"), - "E12", "mt7623", - MTK_EINT_FUNCTION(0, 152), - MTK_FUNCTION(0, "GPIO4"), - MTK_FUNCTION(1, "PWRAP_SPICS_B_I") - ), - MTK_PIN( - PINCTRL_PIN(5, "PWRAP_SPI0_CK2"), - "H11", "mt7623", - MTK_EINT_FUNCTION(0, 155), - MTK_FUNCTION(0, "GPIO5"), - MTK_FUNCTION(1, "PWRAP_SPICK2_I") - ), - MTK_PIN( - PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"), - "G11", "mt7623", - MTK_EINT_FUNCTION(0, 156), - MTK_FUNCTION(0, "GPIO6"), - MTK_FUNCTION(1, "PWRAP_SPICS2_B_I") - ), - MTK_PIN( - PINCTRL_PIN(7, "SPI1_CSN"), - "G19", "mt7623", - MTK_EINT_FUNCTION(0, 153), - MTK_FUNCTION(0, "GPIO7"), - MTK_FUNCTION(1, "SPI1_CS") - ), - MTK_PIN( - PINCTRL_PIN(8, "SPI1_MI"), - "F19", "mt7623", - MTK_EINT_FUNCTION(0, 154), - MTK_FUNCTION(0, "GPIO8"), - MTK_FUNCTION(1, "SPI1_MI"), - MTK_FUNCTION(2, "SPI1_MO") - ), - MTK_PIN( - PINCTRL_PIN(9, "SPI1_MO"), - "G20", "mt7623", - MTK_EINT_FUNCTION(0, 157), - MTK_FUNCTION(0, "GPIO9"), - MTK_FUNCTION(1, "SPI1_MO"), - MTK_FUNCTION(2, "SPI1_MI") - ), - MTK_PIN( - PINCTRL_PIN(10, "RTC32K_CK"), - "A13", "mt7623", - MTK_EINT_FUNCTION(0, 158), - MTK_FUNCTION(0, "GPIO10"), - MTK_FUNCTION(1, "RTC32K_CK") - ), - MTK_PIN( - PINCTRL_PIN(11, "WATCHDOG"), - "D14", "mt7623", - MTK_EINT_FUNCTION(0, 159), - MTK_FUNCTION(0, "GPIO11"), - MTK_FUNCTION(1, "WATCHDOG") - ), - MTK_PIN( - PINCTRL_PIN(12, "SRCLKENA"), - "C13", "mt7623", - MTK_EINT_FUNCTION(0, 169), - MTK_FUNCTION(0, "GPIO12"), - MTK_FUNCTION(1, "SRCLKENA") - ), - MTK_PIN( - PINCTRL_PIN(13, "SRCLKENAI"), - "B13", "mt7623", - MTK_EINT_FUNCTION(0, 161), - MTK_FUNCTION(0, "GPIO13"), - MTK_FUNCTION(1, "SRCLKENAI") - ), - MTK_PIN( - PINCTRL_PIN(14, "GPIO14"), - "E18", "mt7623", - MTK_EINT_FUNCTION(0, 162), - MTK_FUNCTION(0, "GPIO14"), - MTK_FUNCTION(1, "URXD2"), - MTK_FUNCTION(2, "UTXD2") - ), - MTK_PIN( - PINCTRL_PIN(15, "GPIO15"), - "E17", "mt7623", - MTK_EINT_FUNCTION(0, 163), - MTK_FUNCTION(0, "GPIO15"), - MTK_FUNCTION(1, "UTXD2"), - MTK_FUNCTION(2, "URXD2") - ), - MTK_PIN( - PINCTRL_PIN(16, "GPIO16"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO16") - ), - MTK_PIN( - PINCTRL_PIN(17, "GPIO17"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO17") - ), - MTK_PIN( - PINCTRL_PIN(18, "PCM_CLK"), - "C19", "mt7623", - MTK_EINT_FUNCTION(0, 166), - MTK_FUNCTION(0, "GPIO18"), - MTK_FUNCTION(1, "PCM_CLK0"), - MTK_FUNCTION(6, "AP_PCM_CLKO") - ), - MTK_PIN( - PINCTRL_PIN(19, "PCM_SYNC"), - "D19", "mt7623", - MTK_EINT_FUNCTION(0, 167), - MTK_FUNCTION(0, "GPIO19"), - MTK_FUNCTION(1, "PCM_SYNC"), - MTK_FUNCTION(6, "AP_PCM_SYNC") - ), - MTK_PIN( - PINCTRL_PIN(20, "PCM_RX"), - "D18", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO20"), - MTK_FUNCTION(1, "PCM_RX"), - MTK_FUNCTION(4, "PCM_TX"), - MTK_FUNCTION(6, "AP_PCM_RX") - ), - MTK_PIN( - PINCTRL_PIN(21, "PCM_TX"), - "C18", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO21"), - MTK_FUNCTION(1, "PCM_TX"), - MTK_FUNCTION(4, "PCM_RX"), - MTK_FUNCTION(6, "AP_PCM_TX") - ), - MTK_PIN( - PINCTRL_PIN(22, "EINT0"), - "H15", "mt7623", - MTK_EINT_FUNCTION(0, 0), - MTK_FUNCTION(0, "GPIO22"), - MTK_FUNCTION(1, "UCTS0"), - MTK_FUNCTION(2, "PCIE0_PERST_N") - ), - MTK_PIN( - PINCTRL_PIN(23, "EINT1"), - "J16", "mt7623", - MTK_EINT_FUNCTION(0, 1), - MTK_FUNCTION(0, "GPIO23"), - MTK_FUNCTION(1, "URTS0"), - MTK_FUNCTION(2, "PCIE1_PERST_N") - ), - MTK_PIN( - PINCTRL_PIN(24, "EINT2"), - "H16", "mt7623", - MTK_EINT_FUNCTION(0, 2), - MTK_FUNCTION(0, "GPIO24"), - MTK_FUNCTION(1, "UCTS1"), - MTK_FUNCTION(2, "PCIE2_PERST_N") - ), - MTK_PIN( - PINCTRL_PIN(25, "EINT3"), - "K15", "mt7623", - MTK_EINT_FUNCTION(0, 3), - MTK_FUNCTION(0, "GPIO25"), - MTK_FUNCTION(1, "URTS1") - ), - MTK_PIN( - PINCTRL_PIN(26, "EINT4"), - "G15", "mt7623", - MTK_EINT_FUNCTION(0, 4), - MTK_FUNCTION(0, "GPIO26"), - MTK_FUNCTION(1, "UCTS3"), - MTK_FUNCTION(6, "PCIE2_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(27, "EINT5"), - "F15", "mt7623", - MTK_EINT_FUNCTION(0, 5), - MTK_FUNCTION(0, "GPIO27"), - MTK_FUNCTION(1, "URTS3"), - MTK_FUNCTION(6, "PCIE1_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(28, "EINT6"), - "J15", "mt7623", - MTK_EINT_FUNCTION(0, 6), - MTK_FUNCTION(0, "GPIO28"), - MTK_FUNCTION(1, "DRV_VBUS"), - MTK_FUNCTION(6, "PCIE0_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(29, "EINT7"), - "E15", "mt7623", - MTK_EINT_FUNCTION(0, 7), - MTK_FUNCTION(0, "GPIO29"), - MTK_FUNCTION(1, "IDDIG"), - MTK_FUNCTION(2, "MSDC1_WP"), - MTK_FUNCTION(6, "PCIE2_PERST_N") - ), - MTK_PIN( - PINCTRL_PIN(30, "GPIO30"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO30") - ), - MTK_PIN( - PINCTRL_PIN(31, "GPIO31"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO31") - ), - MTK_PIN( - PINCTRL_PIN(32, "GPIO32"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO32") - ), - MTK_PIN( - PINCTRL_PIN(33, "I2S1_DATA"), - "Y18", "mt7623", - MTK_EINT_FUNCTION(0, 15), - MTK_FUNCTION(0, "GPIO33"), - MTK_FUNCTION(1, "I2S1_DATA"), - MTK_FUNCTION(3, "PCM_TX"), - MTK_FUNCTION(6, "AP_PCM_TX") - ), - MTK_PIN( - PINCTRL_PIN(34, "I2S1_DATA_IN"), - "Y17", "mt7623", - MTK_EINT_FUNCTION(0, 16), - MTK_FUNCTION(0, "GPIO34"), - MTK_FUNCTION(1, "I2S1_DATA_IN"), - MTK_FUNCTION(3, "PCM_RX"), - MTK_FUNCTION(6, "AP_PCM_RX") - ), - MTK_PIN( - PINCTRL_PIN(35, "I2S1_BCK"), - "V17", "mt7623", - MTK_EINT_FUNCTION(0, 17), - MTK_FUNCTION(0, "GPIO35"), - MTK_FUNCTION(1, "I2S1_BCK"), - MTK_FUNCTION(3, "PCM_CLK0"), - MTK_FUNCTION(6, "AP_PCM_CLKO") - ), - MTK_PIN( - PINCTRL_PIN(36, "I2S1_LRCK"), - "W17", "mt7623", - MTK_EINT_FUNCTION(0, 18), - MTK_FUNCTION(0, "GPIO36"), - MTK_FUNCTION(1, "I2S1_LRCK"), - MTK_FUNCTION(3, "PCM_SYNC"), - MTK_FUNCTION(6, "AP_PCM_SYNC") - ), - MTK_PIN( - PINCTRL_PIN(37, "I2S1_MCLK"), - "AA18", "mt7623", - MTK_EINT_FUNCTION(0, 19), - MTK_FUNCTION(0, "GPIO37"), - MTK_FUNCTION(1, "I2S1_MCLK") - ), - MTK_PIN( - PINCTRL_PIN(38, "GPIO38"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO38") - ), - MTK_PIN( - PINCTRL_PIN(39, "JTMS"), - "G21", "mt7623", - MTK_EINT_FUNCTION(0, 21), - MTK_FUNCTION(0, "GPIO39"), - MTK_FUNCTION(1, "JTMS") - ), - MTK_PIN( - PINCTRL_PIN(40, "GPIO40"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO40") - ), - MTK_PIN( - PINCTRL_PIN(41, "JTDI"), - "H22", "mt7623", - MTK_EINT_FUNCTION(0, 23), - MTK_FUNCTION(0, "GPIO41"), - MTK_FUNCTION(1, "JTDI") - ), - MTK_PIN( - PINCTRL_PIN(42, "JTDO"), - "H21", "mt7623", - MTK_EINT_FUNCTION(0, 24), - MTK_FUNCTION(0, "GPIO42"), - MTK_FUNCTION(1, "JTDO") - ), - MTK_PIN( - PINCTRL_PIN(43, "NCLE"), - "C7", "mt7623", - MTK_EINT_FUNCTION(0, 25), - MTK_FUNCTION(0, "GPIO43"), - MTK_FUNCTION(1, "NCLE"), - MTK_FUNCTION(2, "EXT_XCS2") - ), - MTK_PIN( - PINCTRL_PIN(44, "NCEB1"), - "C6", "mt7623", - MTK_EINT_FUNCTION(0, 26), - MTK_FUNCTION(0, "GPIO44"), - MTK_FUNCTION(1, "NCEB1"), - MTK_FUNCTION(2, "IDDIG") - ), - MTK_PIN( - PINCTRL_PIN(45, "NCEB0"), - "D7", "mt7623", - MTK_EINT_FUNCTION(0, 27), - MTK_FUNCTION(0, "GPIO45"), - MTK_FUNCTION(1, "NCEB0"), - MTK_FUNCTION(2, "DRV_VBUS") - ), - MTK_PIN( - PINCTRL_PIN(46, "IR"), - "D15", "mt7623", - MTK_EINT_FUNCTION(0, 28), - MTK_FUNCTION(0, "GPIO46"), - MTK_FUNCTION(1, "IR") - ), - MTK_PIN( - PINCTRL_PIN(47, "NREB"), - "A6", "mt7623", - MTK_EINT_FUNCTION(0, 29), - MTK_FUNCTION(0, "GPIO47"), - MTK_FUNCTION(1, "NREB") - ), - MTK_PIN( - PINCTRL_PIN(48, "NRNB"), - "B6", "mt7623", - MTK_EINT_FUNCTION(0, 30), - MTK_FUNCTION(0, "GPIO48"), - MTK_FUNCTION(1, "NRNB") - ), - MTK_PIN( - PINCTRL_PIN(49, "I2S0_DATA"), - "AB18", "mt7623", - MTK_EINT_FUNCTION(0, 31), - MTK_FUNCTION(0, "GPIO49"), - MTK_FUNCTION(1, "I2S0_DATA"), - MTK_FUNCTION(3, "PCM_TX"), - MTK_FUNCTION(6, "AP_I2S_DO") - ), - MTK_PIN( - PINCTRL_PIN(50, "GPIO50"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO50") - ), - MTK_PIN( - PINCTRL_PIN(51, "GPIO51"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO51") - ), - MTK_PIN( - PINCTRL_PIN(52, "GPIO52"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO52") - ), - MTK_PIN( - PINCTRL_PIN(53, "SPI0_CSN"), - "E7", "mt7623", - MTK_EINT_FUNCTION(0, 35), - MTK_FUNCTION(0, "GPIO53"), - MTK_FUNCTION(1, "SPI0_CS"), - MTK_FUNCTION(5, "PWM1") - ), - MTK_PIN( - PINCTRL_PIN(54, "SPI0_CK"), - "F7", "mt7623", - MTK_EINT_FUNCTION(0, 36), - MTK_FUNCTION(0, "GPIO54"), - MTK_FUNCTION(1, "SPI0_CK") - ), - MTK_PIN( - PINCTRL_PIN(55, "SPI0_MI"), - "E6", "mt7623", - MTK_EINT_FUNCTION(0, 37), - MTK_FUNCTION(0, "GPIO55"), - MTK_FUNCTION(1, "SPI0_MI"), - MTK_FUNCTION(2, "SPI0_MO"), - MTK_FUNCTION(3, "MSDC1_WP"), - MTK_FUNCTION(5, "PWM2") - ), - MTK_PIN( - PINCTRL_PIN(56, "SPI0_MO"), - "G7", "mt7623", - MTK_EINT_FUNCTION(0, 38), - MTK_FUNCTION(0, "GPIO56"), - MTK_FUNCTION(1, "SPI0_MO"), - MTK_FUNCTION(2, "SPI0_MI") - ), - MTK_PIN( - PINCTRL_PIN(57, "GPIO57"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO57") - ), - MTK_PIN( - PINCTRL_PIN(58, "GPIO58"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO58") - ), - MTK_PIN( - PINCTRL_PIN(59, "GPIO59"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO59") - ), - MTK_PIN( - PINCTRL_PIN(60, "WB_RSTB"), - "Y21", "mt7623", - MTK_EINT_FUNCTION(0, 41), - MTK_FUNCTION(0, "GPIO60"), - MTK_FUNCTION(1, "WB_RSTB") - ), - MTK_PIN( - PINCTRL_PIN(61, "GPIO61"), - "AA21", "mt7623", - MTK_EINT_FUNCTION(0, 42), - MTK_FUNCTION(0, "GPIO61"), - MTK_FUNCTION(1, "TEST_FD") - ), - MTK_PIN( - PINCTRL_PIN(62, "GPIO62"), - "AB22", "mt7623", - MTK_EINT_FUNCTION(0, 43), - MTK_FUNCTION(0, "GPIO62"), - MTK_FUNCTION(1, "TEST_FC") - ), - MTK_PIN( - PINCTRL_PIN(63, "WB_SCLK"), - "AC23", "mt7623", - MTK_EINT_FUNCTION(0, 44), - MTK_FUNCTION(0, "GPIO63"), - MTK_FUNCTION(1, "WB_SCLK") - ), - MTK_PIN( - PINCTRL_PIN(64, "WB_SDATA"), - "AB21", "mt7623", - MTK_EINT_FUNCTION(0, 45), - MTK_FUNCTION(0, "GPIO64"), - MTK_FUNCTION(1, "WB_SDATA") - ), - MTK_PIN( - PINCTRL_PIN(65, "WB_SEN"), - "AB24", "mt7623", - MTK_EINT_FUNCTION(0, 46), - MTK_FUNCTION(0, "GPIO65"), - MTK_FUNCTION(1, "WB_SEN") - ), - MTK_PIN( - PINCTRL_PIN(66, "WB_CRTL0"), - "AB20", "mt7623", - MTK_EINT_FUNCTION(0, 47), - MTK_FUNCTION(0, "GPIO66"), - MTK_FUNCTION(1, "WB_CRTL0") - ), - MTK_PIN( - PINCTRL_PIN(67, "WB_CRTL1"), - "AC20", "mt7623", - MTK_EINT_FUNCTION(0, 48), - MTK_FUNCTION(0, "GPIO67"), - MTK_FUNCTION(1, "WB_CRTL1") - ), - MTK_PIN( - PINCTRL_PIN(68, "WB_CRTL2"), - "AB19", "mt7623", - MTK_EINT_FUNCTION(0, 49), - MTK_FUNCTION(0, "GPIO68"), - MTK_FUNCTION(1, "WB_CRTL2") - ), - MTK_PIN( - PINCTRL_PIN(69, "WB_CRTL3"), - "AC19", "mt7623", - MTK_EINT_FUNCTION(0, 50), - MTK_FUNCTION(0, "GPIO69"), - MTK_FUNCTION(1, "WB_CRTL3") - ), - MTK_PIN( - PINCTRL_PIN(70, "WB_CRTL4"), - "AD19", "mt7623", - MTK_EINT_FUNCTION(0, 51), - MTK_FUNCTION(0, "GPIO70"), - MTK_FUNCTION(1, "WB_CRTL4") - ), - MTK_PIN( - PINCTRL_PIN(71, "WB_CRTL5"), - "AE19", "mt7623", - MTK_EINT_FUNCTION(0, 52), - MTK_FUNCTION(0, "GPIO71"), - MTK_FUNCTION(1, "WB_CRTL5") - ), - MTK_PIN( - PINCTRL_PIN(72, "I2S0_DATA_IN"), - "AA20", "mt7623", - MTK_EINT_FUNCTION(0, 53), - MTK_FUNCTION(0, "GPIO72"), - MTK_FUNCTION(1, "I2S0_DATA_IN"), - MTK_FUNCTION(3, "PCM_RX"), - MTK_FUNCTION(4, "PWM0"), - MTK_FUNCTION(5, "DISP_PWM"), - MTK_FUNCTION(6, "AP_I2S_DI") - ), - MTK_PIN( - PINCTRL_PIN(73, "I2S0_LRCK"), - "Y20", "mt7623", - MTK_EINT_FUNCTION(0, 54), - MTK_FUNCTION(0, "GPIO73"), - MTK_FUNCTION(1, "I2S0_LRCK"), - MTK_FUNCTION(3, "PCM_SYNC"), - MTK_FUNCTION(6, "AP_I2S_LRCK") - ), - MTK_PIN( - PINCTRL_PIN(74, "I2S0_BCK"), - "Y19", "mt7623", - MTK_EINT_FUNCTION(0, 55), - MTK_FUNCTION(0, "GPIO74"), - MTK_FUNCTION(1, "I2S0_BCK"), - MTK_FUNCTION(3, "PCM_CLK0"), - MTK_FUNCTION(6, "AP_I2S_BCK") - ), - MTK_PIN( - PINCTRL_PIN(75, "SDA0"), - "K19", "mt7623", - MTK_EINT_FUNCTION(0, 56), - MTK_FUNCTION(0, "GPIO75"), - MTK_FUNCTION(1, "SDA0") - ), - MTK_PIN( - PINCTRL_PIN(76, "SCL0"), - "K20", "mt7623", - MTK_EINT_FUNCTION(0, 57), - MTK_FUNCTION(0, "GPIO76"), - MTK_FUNCTION(1, "SCL0") - ), - MTK_PIN( - PINCTRL_PIN(77, "GPIO77"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO77") - ), - MTK_PIN( - PINCTRL_PIN(78, "GPIO78"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO78") - ), - MTK_PIN( - PINCTRL_PIN(79, "GPIO79"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO79") - ), - MTK_PIN( - PINCTRL_PIN(80, "GPIO80"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO80") - ), - MTK_PIN( - PINCTRL_PIN(81, "GPIO81"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO81") - ), - MTK_PIN( - PINCTRL_PIN(82, "GPIO82"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO82") - ), - MTK_PIN( - PINCTRL_PIN(83, "LCM_RST"), - "V16", "mt7623", - MTK_EINT_FUNCTION(0, 64), - MTK_FUNCTION(0, "GPIO83"), - MTK_FUNCTION(1, "LCM_RST") - ), - MTK_PIN( - PINCTRL_PIN(84, "DSI_TE"), - "V14", "mt7623", - MTK_EINT_FUNCTION(0, 65), - MTK_FUNCTION(0, "GPIO84"), - MTK_FUNCTION(1, "DSI_TE") - ), - MTK_PIN( - PINCTRL_PIN(85, "GPIO85"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO85") - ), - MTK_PIN( - PINCTRL_PIN(86, "GPIO86"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO86") - ), - MTK_PIN( - PINCTRL_PIN(87, "GPIO87"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO87") - ), - MTK_PIN( - PINCTRL_PIN(88, "GPIO88"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO88") - ), - MTK_PIN( - PINCTRL_PIN(89, "GPIO89"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO89") - ), - MTK_PIN( - PINCTRL_PIN(90, "GPIO90"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO90") - ), - MTK_PIN( - PINCTRL_PIN(91, "GPIO91"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO91") - ), - MTK_PIN( - PINCTRL_PIN(92, "GPIO92"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO92") - ), - MTK_PIN( - PINCTRL_PIN(93, "GPIO93"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO93") - ), - MTK_PIN( - PINCTRL_PIN(94, "GPIO94"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO94") - ), - MTK_PIN( - PINCTRL_PIN(95, "MIPI_TCN"), - "AB14", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO95"), - MTK_FUNCTION(1, "TCN") - ), - MTK_PIN( - PINCTRL_PIN(96, "MIPI_TCP"), - "AC14", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO96"), - MTK_FUNCTION(1, "TCP") - ), - MTK_PIN( - PINCTRL_PIN(97, "MIPI_TDN1"), - "AE15", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO97"), - MTK_FUNCTION(1, "TDN1") - ), - MTK_PIN( - PINCTRL_PIN(98, "MIPI_TDP1"), - "AD15", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO98"), - MTK_FUNCTION(1, "TDP1") - ), - MTK_PIN( - PINCTRL_PIN(99, "MIPI_TDN0"), - "AB15", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO99"), - MTK_FUNCTION(1, "TDN0") - ), - MTK_PIN( - PINCTRL_PIN(100, "MIPI_TDP0"), - "AC15", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO100"), - MTK_FUNCTION(1, "TDP0") - ), - MTK_PIN( - PINCTRL_PIN(101, "GPIO101"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO101") - ), - MTK_PIN( - PINCTRL_PIN(102, "GPIO102"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO102") - ), - MTK_PIN( - PINCTRL_PIN(103, "GPIO103"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO103") - ), - MTK_PIN( - PINCTRL_PIN(104, "GPIO104"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO104") - ), - MTK_PIN( - PINCTRL_PIN(105, "MSDC1_CMD"), - "AD2", "mt7623", - MTK_EINT_FUNCTION(0, 78), - MTK_FUNCTION(0, "GPIO105"), - MTK_FUNCTION(1, "MSDC1_CMD"), - MTK_FUNCTION(3, "SDA1"), - MTK_FUNCTION(6, "I2SOUT_BCK") - ), - MTK_PIN( - PINCTRL_PIN(106, "MSDC1_CLK"), - "AD3", "mt7623", - MTK_EINT_FUNCTION(0, 79), - MTK_FUNCTION(0, "GPIO106"), - MTK_FUNCTION(1, "MSDC1_CLK"), - MTK_FUNCTION(3, "SCL1"), - MTK_FUNCTION(6, "I2SOUT_LRCK") - ), - MTK_PIN( - PINCTRL_PIN(107, "MSDC1_DAT0"), - "AE2", "mt7623", - MTK_EINT_FUNCTION(0, 80), - MTK_FUNCTION(0, "GPIO107"), - MTK_FUNCTION(1, "MSDC1_DAT0"), - MTK_FUNCTION(5, "UTXD0"), - MTK_FUNCTION(6, "I2SOUT_DATA_OUT") - ), - MTK_PIN( - PINCTRL_PIN(108, "MSDC1_DAT1"), - "AC1", "mt7623", - MTK_EINT_FUNCTION(0, 81), - MTK_FUNCTION(0, "GPIO108"), - MTK_FUNCTION(1, "MSDC1_DAT1"), - MTK_FUNCTION(3, "PWM0"), - MTK_FUNCTION(5, "URXD0"), - MTK_FUNCTION(6, "PWM1") - ), - MTK_PIN( - PINCTRL_PIN(109, "MSDC1_DAT2"), - "AC3", "mt7623", - MTK_EINT_FUNCTION(0, 82), - MTK_FUNCTION(0, "GPIO109"), - MTK_FUNCTION(1, "MSDC1_DAT2"), - MTK_FUNCTION(3, "SDA2"), - MTK_FUNCTION(5, "UTXD1"), - MTK_FUNCTION(6, "PWM2") - ), - MTK_PIN( - PINCTRL_PIN(110, "MSDC1_DAT3"), - "AC4", "mt7623", - MTK_EINT_FUNCTION(0, 83), - MTK_FUNCTION(0, "GPIO110"), - MTK_FUNCTION(1, "MSDC1_DAT3"), - MTK_FUNCTION(3, "SCL2"), - MTK_FUNCTION(5, "URXD1"), - MTK_FUNCTION(6, "PWM3") - ), - MTK_PIN( - PINCTRL_PIN(111, "MSDC0_DAT7"), - "A2", "mt7623", - MTK_EINT_FUNCTION(0, 84), - MTK_FUNCTION(0, "GPIO111"), - MTK_FUNCTION(1, "MSDC0_DAT7"), - MTK_FUNCTION(4, "NLD7") - ), - MTK_PIN( - PINCTRL_PIN(112, "MSDC0_DAT6"), - "B3", "mt7623", - MTK_EINT_FUNCTION(0, 85), - MTK_FUNCTION(0, "GPIO112"), - MTK_FUNCTION(1, "MSDC0_DAT6"), - MTK_FUNCTION(4, "NLD6") - ), - MTK_PIN( - PINCTRL_PIN(113, "MSDC0_DAT5"), - "C4", "mt7623", - MTK_EINT_FUNCTION(0, 86), - MTK_FUNCTION(0, "GPIO113"), - MTK_FUNCTION(1, "MSDC0_DAT5"), - MTK_FUNCTION(4, "NLD5") - ), - MTK_PIN( - PINCTRL_PIN(114, "MSDC0_DAT4"), - "A4", "mt7623", - MTK_EINT_FUNCTION(0, 87), - MTK_FUNCTION(0, "GPIO114"), - MTK_FUNCTION(1, "MSDC0_DAT4"), - MTK_FUNCTION(4, "NLD4") - ), - MTK_PIN( - PINCTRL_PIN(115, "MSDC0_RSTB"), - "C5", "mt7623", - MTK_EINT_FUNCTION(0, 88), - MTK_FUNCTION(0, "GPIO115"), - MTK_FUNCTION(1, "MSDC0_RSTB"), - MTK_FUNCTION(4, "NLD8") - ), - MTK_PIN( - PINCTRL_PIN(116, "MSDC0_CMD"), - "D5", "mt7623", - MTK_EINT_FUNCTION(0, 89), - MTK_FUNCTION(0, "GPIO116"), - MTK_FUNCTION(1, "MSDC0_CMD"), - MTK_FUNCTION(4, "NALE") - ), - MTK_PIN( - PINCTRL_PIN(117, "MSDC0_CLK"), - "B1", "mt7623", - MTK_EINT_FUNCTION(0, 90), - MTK_FUNCTION(0, "GPIO117"), - MTK_FUNCTION(1, "MSDC0_CLK"), - MTK_FUNCTION(4, "NWEB") - ), - MTK_PIN( - PINCTRL_PIN(118, "MSDC0_DAT3"), - "D6", "mt7623", - MTK_EINT_FUNCTION(0, 91), - MTK_FUNCTION(0, "GPIO118"), - MTK_FUNCTION(1, "MSDC0_DAT3"), - MTK_FUNCTION(4, "NLD3") - ), - MTK_PIN( - PINCTRL_PIN(119, "MSDC0_DAT2"), - "B2", "mt7623", - MTK_EINT_FUNCTION(0, 92), - MTK_FUNCTION(0, "GPIO119"), - MTK_FUNCTION(1, "MSDC0_DAT2"), - MTK_FUNCTION(4, "NLD2") - ), - MTK_PIN( - PINCTRL_PIN(120, "MSDC0_DAT1"), - "A3", "mt7623", - MTK_EINT_FUNCTION(0, 93), - MTK_FUNCTION(0, "GPIO120"), - MTK_FUNCTION(1, "MSDC0_DAT1"), - MTK_FUNCTION(4, "NLD1") - ), - MTK_PIN( - PINCTRL_PIN(121, "MSDC0_DAT0"), - "B4", "mt7623", - MTK_EINT_FUNCTION(0, 94), - MTK_FUNCTION(0, "GPIO121"), - MTK_FUNCTION(1, "MSDC0_DAT0"), - MTK_FUNCTION(4, "NLD0"), - MTK_FUNCTION(5, "WATCHDOG") - ), - MTK_PIN( - PINCTRL_PIN(122, "GPIO122"), - "H17", "mt7623", - MTK_EINT_FUNCTION(0, 95), - MTK_FUNCTION(0, "GPIO122"), - MTK_FUNCTION(1, "TEST"), - MTK_FUNCTION(4, "SDA2"), - MTK_FUNCTION(5, "URXD0") - ), - MTK_PIN( - PINCTRL_PIN(123, "GPIO123"), - "F17", "mt7623", - MTK_EINT_FUNCTION(0, 96), - MTK_FUNCTION(0, "GPIO123"), - MTK_FUNCTION(1, "TEST"), - MTK_FUNCTION(4, "SCL2"), - MTK_FUNCTION(5, "UTXD0") - ), - MTK_PIN( - PINCTRL_PIN(124, "GPIO124"), - "H18", "mt7623", - MTK_EINT_FUNCTION(0, 97), - MTK_FUNCTION(0, "GPIO124"), - MTK_FUNCTION(1, "TEST"), - MTK_FUNCTION(4, "SDA1"), - MTK_FUNCTION(5, "PWM3") - ), - MTK_PIN( - PINCTRL_PIN(125, "GPIO125"), - "G17", "mt7623", - MTK_EINT_FUNCTION(0, 98), - MTK_FUNCTION(0, "GPIO125"), - MTK_FUNCTION(1, "TEST"), - MTK_FUNCTION(4, "SCL1"), - MTK_FUNCTION(5, "PWM4") - ), - MTK_PIN( - PINCTRL_PIN(126, "I2S0_MCLK"), - "AA19", "mt7623", - MTK_EINT_FUNCTION(0, 99), - MTK_FUNCTION(0, "GPIO126"), - MTK_FUNCTION(1, "I2S0_MCLK"), - MTK_FUNCTION(6, "AP_I2S_MCLK") - ), - MTK_PIN( - PINCTRL_PIN(127, "GPIO127"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO127") - ), - MTK_PIN( - PINCTRL_PIN(128, "GPIO128"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO128") - ), - MTK_PIN( - PINCTRL_PIN(129, "GPIO129"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO129") - ), - MTK_PIN( - PINCTRL_PIN(130, "GPIO130"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO130") - ), - MTK_PIN( - PINCTRL_PIN(131, "GPIO131"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO131") - ), - MTK_PIN( - PINCTRL_PIN(132, "GPIO132"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO132") - ), - MTK_PIN( - PINCTRL_PIN(133, "GPIO133"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO133") - ), - MTK_PIN( - PINCTRL_PIN(134, "GPIO134"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO134") - ), - MTK_PIN( - PINCTRL_PIN(135, "GPIO135"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO135") - ), - MTK_PIN( - PINCTRL_PIN(136, "GPIO136"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO136") - ), - MTK_PIN( - PINCTRL_PIN(137, "GPIO137"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO137") - ), - MTK_PIN( - PINCTRL_PIN(138, "GPIO138"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO138") - ), - MTK_PIN( - PINCTRL_PIN(139, "GPIO139"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO139") - ), - MTK_PIN( - PINCTRL_PIN(140, "GPIO140"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO140") - ), - MTK_PIN( - PINCTRL_PIN(141, "GPIO141"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO141") - ), - MTK_PIN( - PINCTRL_PIN(142, "GPIO142"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO142") - ), - MTK_PIN( - PINCTRL_PIN(143, "GPIO143"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO143") - ), - MTK_PIN( - PINCTRL_PIN(144, "GPIO144"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO144") - ), - MTK_PIN( - PINCTRL_PIN(145, "GPIO145"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO145") - ), - MTK_PIN( - PINCTRL_PIN(146, "GPIO146"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO146") - ), - MTK_PIN( - PINCTRL_PIN(147, "GPIO147"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO147") - ), - MTK_PIN( - PINCTRL_PIN(148, "GPIO148"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO148") - ), - MTK_PIN( - PINCTRL_PIN(149, "GPIO149"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO149") - ), - MTK_PIN( - PINCTRL_PIN(150, "GPIO150"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO150") - ), - MTK_PIN( - PINCTRL_PIN(151, "GPIO151"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO151") - ), - MTK_PIN( - PINCTRL_PIN(152, "GPIO152"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO152") - ), - MTK_PIN( - PINCTRL_PIN(153, "GPIO153"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO153") - ), - MTK_PIN( - PINCTRL_PIN(154, "GPIO154"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO154") - ), - MTK_PIN( - PINCTRL_PIN(155, "GPIO155"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO155") - ), - MTK_PIN( - PINCTRL_PIN(156, "GPIO156"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO156") - ), - MTK_PIN( - PINCTRL_PIN(157, "GPIO157"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO157") - ), - MTK_PIN( - PINCTRL_PIN(158, "GPIO158"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO158") - ), - MTK_PIN( - PINCTRL_PIN(159, "GPIO159"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO159") - ), - MTK_PIN( - PINCTRL_PIN(160, "GPIO160"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO160") - ), - MTK_PIN( - PINCTRL_PIN(161, "GPIO161"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO161") - ), - MTK_PIN( - PINCTRL_PIN(162, "GPIO162"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO162") - ), - MTK_PIN( - PINCTRL_PIN(163, "GPIO163"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO163") - ), - MTK_PIN( - PINCTRL_PIN(164, "GPIO164"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO164") - ), - MTK_PIN( - PINCTRL_PIN(165, "GPIO165"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO165") - ), - MTK_PIN( - PINCTRL_PIN(166, "GPIO166"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO166") - ), - MTK_PIN( - PINCTRL_PIN(167, "GPIO167"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO167") - ), - MTK_PIN( - PINCTRL_PIN(168, "GPIO168"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO168") - ), - MTK_PIN( - PINCTRL_PIN(169, "GPIO169"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO169") - ), - MTK_PIN( - PINCTRL_PIN(170, "GPIO170"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO170") - ), - MTK_PIN( - PINCTRL_PIN(171, "GPIO171"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO171") - ), - MTK_PIN( - PINCTRL_PIN(172, "GPIO172"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO172") - ), - MTK_PIN( - PINCTRL_PIN(173, "GPIO173"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO173") - ), - MTK_PIN( - PINCTRL_PIN(174, "GPIO174"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO174") - ), - MTK_PIN( - PINCTRL_PIN(175, "GPIO175"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO175") - ), - MTK_PIN( - PINCTRL_PIN(176, "GPIO176"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO176") - ), - MTK_PIN( - PINCTRL_PIN(177, "GPIO177"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO177") - ), - MTK_PIN( - PINCTRL_PIN(178, "GPIO178"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO178") - ), - MTK_PIN( - PINCTRL_PIN(179, "GPIO179"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO179") - ), - MTK_PIN( - PINCTRL_PIN(180, "GPIO180"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO180") - ), - MTK_PIN( - PINCTRL_PIN(181, "GPIO181"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO181") - ), - MTK_PIN( - PINCTRL_PIN(182, "GPIO182"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO182") - ), - MTK_PIN( - PINCTRL_PIN(183, "GPIO183"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO183") - ), - MTK_PIN( - PINCTRL_PIN(184, "GPIO184"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO184") - ), - MTK_PIN( - PINCTRL_PIN(185, "GPIO185"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO185") - ), - MTK_PIN( - PINCTRL_PIN(186, "GPIO186"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO186") - ), - MTK_PIN( - PINCTRL_PIN(187, "GPIO187"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO187") - ), - MTK_PIN( - PINCTRL_PIN(188, "GPIO188"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO188") - ), - MTK_PIN( - PINCTRL_PIN(189, "GPIO189"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO189") - ), - MTK_PIN( - PINCTRL_PIN(190, "GPIO190"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO190") - ), - MTK_PIN( - PINCTRL_PIN(191, "GPIO191"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO191") - ), - MTK_PIN( - PINCTRL_PIN(192, "GPIO192"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO192") - ), - MTK_PIN( - PINCTRL_PIN(193, "GPIO193"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO193") - ), - MTK_PIN( - PINCTRL_PIN(194, "GPIO194"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO194") - ), - MTK_PIN( - PINCTRL_PIN(195, "GPIO195"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO195") - ), - MTK_PIN( - PINCTRL_PIN(196, "GPIO196"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO196") - ), - MTK_PIN( - PINCTRL_PIN(197, "GPIO197"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO197") - ), - MTK_PIN( - PINCTRL_PIN(198, "GPIO198"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO198") - ), - MTK_PIN( - PINCTRL_PIN(199, "SPI1_CK"), - "E19", "mt7623", - MTK_EINT_FUNCTION(0, 111), - MTK_FUNCTION(0, "GPIO199"), - MTK_FUNCTION(1, "SPI1_CK") - ), - MTK_PIN( - PINCTRL_PIN(200, "URXD2"), - "K18", "mt7623", - MTK_EINT_FUNCTION(0, 112), - MTK_FUNCTION(0, "GPIO200"), - MTK_FUNCTION(6, "URXD2") - ), - MTK_PIN( - PINCTRL_PIN(201, "UTXD2"), - "L18", "mt7623", - MTK_EINT_FUNCTION(0, 113), - MTK_FUNCTION(0, "GPIO201"), - MTK_FUNCTION(6, "UTXD2") - ), - MTK_PIN( - PINCTRL_PIN(202, "GPIO202"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO202") - ), - MTK_PIN( - PINCTRL_PIN(203, "PWM0"), - "AA16", "mt7623", - MTK_EINT_FUNCTION(0, 115), - MTK_FUNCTION(0, "GPIO203"), - MTK_FUNCTION(1, "PWM0"), - MTK_FUNCTION(2, "DISP_PWM") - ), - MTK_PIN( - PINCTRL_PIN(204, "PWM1"), - "Y16", "mt7623", - MTK_EINT_FUNCTION(0, 116), - MTK_FUNCTION(0, "GPIO204"), - MTK_FUNCTION(1, "PWM1") - ), - MTK_PIN( - PINCTRL_PIN(205, "PWM2"), - "AA15", "mt7623", - MTK_EINT_FUNCTION(0, 117), - MTK_FUNCTION(0, "GPIO205"), - MTK_FUNCTION(1, "PWM2") - ), - MTK_PIN( - PINCTRL_PIN(206, "PWM3"), - "AA17", "mt7623", - MTK_EINT_FUNCTION(0, 118), - MTK_FUNCTION(0, "GPIO206"), - MTK_FUNCTION(1, "PWM3") - ), - MTK_PIN( - PINCTRL_PIN(207, "PWM4"), - "Y15", "mt7623", - MTK_EINT_FUNCTION(0, 119), - MTK_FUNCTION(0, "GPIO207"), - MTK_FUNCTION(1, "PWM4") - ), - MTK_PIN( - PINCTRL_PIN(208, "AUD_EXT_CK1"), - "W14", "mt7623", - MTK_EINT_FUNCTION(0, 120), - MTK_FUNCTION(0, "GPIO208"), - MTK_FUNCTION(1, "AUD_EXT_CK1"), - MTK_FUNCTION(2, "PWM0"), - MTK_FUNCTION(3, "PCIE0_PERST_N"), - MTK_FUNCTION(5, "DISP_PWM") - ), - MTK_PIN( - PINCTRL_PIN(209, "AUD_EXT_CK2"), - "V15", "mt7623", - MTK_EINT_FUNCTION(0, 121), - MTK_FUNCTION(0, "GPIO209"), - MTK_FUNCTION(1, "AUD_EXT_CK2"), - MTK_FUNCTION(2, "MSDC1_WP"), - MTK_FUNCTION(3, "PCIE1_PERST_N"), - MTK_FUNCTION(5, "PWM1") - ), - MTK_PIN( - PINCTRL_PIN(210, "GPIO210"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO210") - ), - MTK_PIN( - PINCTRL_PIN(211, "GPIO211"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO211") - ), - MTK_PIN( - PINCTRL_PIN(212, "GPIO212"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO212") - ), - MTK_PIN( - PINCTRL_PIN(213, "GPIO213"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO213") - ), - MTK_PIN( - PINCTRL_PIN(214, "GPIO214"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO214") - ), - MTK_PIN( - PINCTRL_PIN(215, "GPIO215"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO215") - ), - MTK_PIN( - PINCTRL_PIN(216, "GPIO216"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO216") - ), - MTK_PIN( - PINCTRL_PIN(217, "GPIO217"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO217") - ), - MTK_PIN( - PINCTRL_PIN(218, "GPIO218"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO218") - ), - MTK_PIN( - PINCTRL_PIN(219, "GPIO219"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO219") - ), - MTK_PIN( - PINCTRL_PIN(220, "GPIO220"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO220") - ), - MTK_PIN( - PINCTRL_PIN(221, "GPIO221"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO221") - ), - MTK_PIN( - PINCTRL_PIN(222, "GPIO222"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO222") - ), - MTK_PIN( - PINCTRL_PIN(223, "GPIO223"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO223") - ), - MTK_PIN( - PINCTRL_PIN(224, "GPIO224"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO224") - ), - MTK_PIN( - PINCTRL_PIN(225, "GPIO225"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO225") - ), - MTK_PIN( - PINCTRL_PIN(226, "GPIO226"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO226") - ), - MTK_PIN( - PINCTRL_PIN(227, "GPIO227"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO227") - ), - MTK_PIN( - PINCTRL_PIN(228, "GPIO228"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO228") - ), - MTK_PIN( - PINCTRL_PIN(229, "GPIO229"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO229") - ), - MTK_PIN( - PINCTRL_PIN(230, "GPIO230"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO230") - ), - MTK_PIN( - PINCTRL_PIN(231, "GPIO231"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO231") - ), - MTK_PIN( - PINCTRL_PIN(232, "GPIO232"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO232") - ), - MTK_PIN( - PINCTRL_PIN(233, "GPIO233"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO233") - ), - MTK_PIN( - PINCTRL_PIN(234, "GPIO234"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO234") - ), - MTK_PIN( - PINCTRL_PIN(235, "GPIO235"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO235") - ), - MTK_PIN( - PINCTRL_PIN(236, "EXT_SDIO3"), - "A8", "mt7623", - MTK_EINT_FUNCTION(0, 122), - MTK_FUNCTION(0, "GPIO236"), - MTK_FUNCTION(1, "EXT_SDIO3"), - MTK_FUNCTION(2, "IDDIG") - ), - MTK_PIN( - PINCTRL_PIN(237, "EXT_SDIO2"), - "D8", "mt7623", - MTK_EINT_FUNCTION(0, 123), - MTK_FUNCTION(0, "GPIO237"), - MTK_FUNCTION(1, "EXT_SDIO2"), - MTK_FUNCTION(2, "DRV_VBUS") - ), - MTK_PIN( - PINCTRL_PIN(238, "EXT_SDIO1"), - "D9", "mt7623", - MTK_EINT_FUNCTION(0, 124), - MTK_FUNCTION(0, "GPIO238"), - MTK_FUNCTION(1, "EXT_SDIO1") - ), - MTK_PIN( - PINCTRL_PIN(239, "EXT_SDIO0"), - "B8", "mt7623", - MTK_EINT_FUNCTION(0, 125), - MTK_FUNCTION(0, "GPIO239"), - MTK_FUNCTION(1, "EXT_SDIO0") - ), - MTK_PIN( - PINCTRL_PIN(240, "EXT_XCS"), - "C9", "mt7623", - MTK_EINT_FUNCTION(0, 126), - MTK_FUNCTION(0, "GPIO240"), - MTK_FUNCTION(1, "EXT_XCS") - ), - MTK_PIN( - PINCTRL_PIN(241, "EXT_SCK"), - "C8", "mt7623", - MTK_EINT_FUNCTION(0, 127), - MTK_FUNCTION(0, "GPIO241"), - MTK_FUNCTION(1, "EXT_SCK") - ), - MTK_PIN( - PINCTRL_PIN(242, "URTS2"), - "G18", "mt7623", - MTK_EINT_FUNCTION(0, 128), - MTK_FUNCTION(0, "GPIO242"), - MTK_FUNCTION(1, "URTS2"), - MTK_FUNCTION(2, "UTXD3"), - MTK_FUNCTION(3, "URXD3"), - MTK_FUNCTION(4, "SCL1") - ), - MTK_PIN( - PINCTRL_PIN(243, "UCTS2"), - "H19", "mt7623", - MTK_EINT_FUNCTION(0, 129), - MTK_FUNCTION(0, "GPIO243"), - MTK_FUNCTION(1, "UCTS2"), - MTK_FUNCTION(2, "URXD3"), - MTK_FUNCTION(3, "UTXD3"), - MTK_FUNCTION(4, "SDA1") - ), - MTK_PIN( - PINCTRL_PIN(244, "GPIO244"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO244") - ), - MTK_PIN( - PINCTRL_PIN(245, "GPIO245"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO245") - ), - MTK_PIN( - PINCTRL_PIN(246, "GPIO246"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO246") - ), - MTK_PIN( - PINCTRL_PIN(247, "GPIO247"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO247") - ), - MTK_PIN( - PINCTRL_PIN(248, "GPIO248"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO248") - ), - MTK_PIN( - PINCTRL_PIN(249, "GPIO249"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO249") - ), - MTK_PIN( - PINCTRL_PIN(250, "GPIO250"), - "A15", "mt7623", - MTK_EINT_FUNCTION(0, 135), - MTK_FUNCTION(0, "GPIO250"), - MTK_FUNCTION(1, "TEST_MD7"), - MTK_FUNCTION(6, "PCIE0_CLKREQ_N") - ), - MTK_PIN( - PINCTRL_PIN(251, "GPIO251"), - "B15", "mt7623", - MTK_EINT_FUNCTION(0, 136), - MTK_FUNCTION(0, "GPIO251"), - MTK_FUNCTION(1, "TEST_MD6"), - MTK_FUNCTION(6, "PCIE0_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(252, "GPIO252"), - "C16", "mt7623", - MTK_EINT_FUNCTION(0, 137), - MTK_FUNCTION(0, "GPIO252"), - MTK_FUNCTION(1, "TEST_MD5"), - MTK_FUNCTION(6, "PCIE1_CLKREQ_N") - ), - MTK_PIN( - PINCTRL_PIN(253, "GPIO253"), - "D17", "mt7623", - MTK_EINT_FUNCTION(0, 138), - MTK_FUNCTION(0, "GPIO253"), - MTK_FUNCTION(1, "TEST_MD4"), - MTK_FUNCTION(6, "PCIE1_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(254, "GPIO254"), - "D16", "mt7623", - MTK_EINT_FUNCTION(0, 139), - MTK_FUNCTION(0, "GPIO254"), - MTK_FUNCTION(1, "TEST_MD3"), - MTK_FUNCTION(6, "PCIE2_CLKREQ_N") - ), - MTK_PIN( - PINCTRL_PIN(255, "GPIO255"), - "C17", "mt7623", - MTK_EINT_FUNCTION(0, 140), - MTK_FUNCTION(0, "GPIO255"), - MTK_FUNCTION(1, "TEST_MD2"), - MTK_FUNCTION(6, "PCIE2_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(256, "GPIO256"), - "B17", "mt7623", - MTK_EINT_FUNCTION(0, 141), - MTK_FUNCTION(0, "GPIO256"), - MTK_FUNCTION(1, "TEST_MD1") - ), - MTK_PIN( - PINCTRL_PIN(257, "GPIO257"), - "C15", "mt7623", - MTK_EINT_FUNCTION(0, 142), - MTK_FUNCTION(0, "GPIO257"), - MTK_FUNCTION(1, "TEST_MD0") - ), - MTK_PIN( - PINCTRL_PIN(258, "GPIO258"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO258") - ), - MTK_PIN( - PINCTRL_PIN(259, "GPIO259"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO259") - ), - MTK_PIN( - PINCTRL_PIN(260, "GPIO260"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO260") - ), - MTK_PIN( - PINCTRL_PIN(261, "MSDC1_INS"), - "AD1", "mt7623", - MTK_EINT_FUNCTION(0, 146), - MTK_FUNCTION(0, "GPIO261"), - MTK_FUNCTION(1, "MSDC1_INS") - ), - MTK_PIN( - PINCTRL_PIN(262, "G2_TXEN"), - "A23", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO262"), - MTK_FUNCTION(1, "G2_TXEN") - ), - MTK_PIN( - PINCTRL_PIN(263, "G2_TXD3"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO263"), - MTK_FUNCTION(1, "G2_TXD3") - ), - MTK_PIN( - PINCTRL_PIN(264, "G2_TXD2"), - "C24", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO264"), - MTK_FUNCTION(1, "G2_TXD2") - ), - MTK_PIN( - PINCTRL_PIN(265, "G2_TXD1"), - "B25", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO265"), - MTK_FUNCTION(1, "G2_TXD1") - ), - MTK_PIN( - PINCTRL_PIN(266, "G2_TXD0"), - "A24", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO266"), - MTK_FUNCTION(1, "G2_TXD0") - ), - MTK_PIN( - PINCTRL_PIN(267, "G2_TXCLK"), - "C23", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO267"), - MTK_FUNCTION(1, "G2_TXC") - ), - MTK_PIN( - PINCTRL_PIN(268, "G2_RXCLK"), - "B23", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO268"), - MTK_FUNCTION(1, "G2_RXC") - ), - MTK_PIN( - PINCTRL_PIN(269, "G2_RXD0"), - "D21", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO269"), - MTK_FUNCTION(1, "G2_RXD0") - ), - MTK_PIN( - PINCTRL_PIN(270, "G2_RXD1"), - "B22", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO270"), - MTK_FUNCTION(1, "G2_RXD1") - ), - MTK_PIN( - PINCTRL_PIN(271, "G2_RXD2"), - "A22", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO271"), - MTK_FUNCTION(1, "G2_RXD2") - ), - MTK_PIN( - PINCTRL_PIN(272, "G2_RXD3"), - "C22", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO272"), - MTK_FUNCTION(1, "G2_RXD3") - ), - MTK_PIN( - PINCTRL_PIN(273, "GPIO273"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO273") - ), - MTK_PIN( - PINCTRL_PIN(274, "G2_RXDV"), - "C21", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO274"), - MTK_FUNCTION(1, "G2_RXDV") - ), - MTK_PIN( - PINCTRL_PIN(275, "G2_MDC"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO275"), - MTK_FUNCTION(1, "MDC") - ), - MTK_PIN( - PINCTRL_PIN(276, "G2_MDIO"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO276"), - MTK_FUNCTION(1, "MDIO") - ), - MTK_PIN( - PINCTRL_PIN(277, "GPIO277"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO277") - ), - MTK_PIN( - PINCTRL_PIN(278, "JTAG_RESET"), - "H20", "mt7623", - MTK_EINT_FUNCTION(0, 147), - MTK_FUNCTION(0, "GPIO278"), - MTK_FUNCTION(1, "JTAG_RESET") - ), -}; - -#endif /* __PINCTRL_MTK_MT7623_H */ diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c index 07f1cb21c1b8..e1bdf1f3b75c 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8.c +++ b/drivers/pinctrl/meson/pinctrl-meson8.c @@ -205,6 +205,9 @@ static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; +static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int pwm_b_x_pins[] = { PIN(GPIOX_11, 0) }; + /* bank Y */ static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) }; static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) }; @@ -219,6 +222,20 @@ static const unsigned int pcm_clk_b_pins[] = { PIN(GPIOY_7, 0) }; static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) }; static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) }; +static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, 0) }; + +static const unsigned int i2s_out_ch45_pins[] = { PIN(GPIOY_0, 0) }; +static const unsigned int i2s_out_ch23_pins[] = { PIN(GPIOY_1, 0) }; +static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOY_4, 0) }; +static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOY_5, 0) }; +static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOY_6, 0) }; +static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOY_7, 0) }; +static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOY_8, 0) }; +static const unsigned int i2s_out_ch78_pins[] = { PIN(GPIOY_9, 0) }; + +static const unsigned int spdif_in_pins[] = { PIN(GPIOY_2, 0) }; +static const unsigned int spdif_out_pins[] = { PIN(GPIOY_3, 0) }; + /* bank DV */ static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0), PIN(GPIODV_2, 0), PIN(GPIODV_3, 0), @@ -264,6 +281,10 @@ static const unsigned int uart_rts_b1_pins[] = { PIN(GPIODV_27, 0) }; static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) }; static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) }; +static const unsigned int pwm_c_dv9_pins[] = { PIN(GPIODV_9, 0) }; +static const unsigned int pwm_c_dv29_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) }; + /* bank H */ static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; @@ -312,6 +333,11 @@ static const unsigned int i2c_sck_a1_pins[] = { PIN(GPIOZ_1, 0) }; static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) }; static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) }; +static const unsigned int pwm_a_z0_pins[] = { PIN(GPIOZ_0, 0) }; +static const unsigned int pwm_a_z7_pins[] = { PIN(GPIOZ_7, 0) }; +static const unsigned int pwm_b_z_pins[] = { PIN(GPIOZ_1, 0) }; +static const unsigned int pwm_c_z_pins[] = { PIN(GPIOZ_8, 0) }; + /* bank BOOT */ static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; @@ -369,6 +395,7 @@ static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; +static const unsigned int remote_output_ao_pins[] = { PIN(GPIOAO_13, AO_OFF) }; static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; @@ -382,6 +409,15 @@ static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int pwm_f_ao_pins[] = { PIN(GPIO_TEST_N, AO_OFF) }; + +static const unsigned int i2s_am_clk_out_ao_pins[] = { PIN(GPIOAO_8, AO_OFF) }; +static const unsigned int i2s_ao_clk_out_ao_pins[] = { PIN(GPIOAO_9, AO_OFF) }; +static const unsigned int i2s_lr_clk_out_ao_pins[] = { PIN(GPIOAO_10, AO_OFF) }; +static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, AO_OFF) }; + +static const unsigned int hdmi_cec_ao_pins[] = { PIN(GPIOAO_12, AO_OFF) }; + static struct meson_pmx_group meson8_cbus_groups[] = { GPIO_GROUP(GPIOX_0, 0), GPIO_GROUP(GPIOX_1, 0), @@ -523,6 +559,9 @@ static struct meson_pmx_group meson8_cbus_groups[] = { GROUP(xtal_32k_out, 3, 22), GROUP(xtal_24m_out, 3, 23), + GROUP(pwm_e, 9, 19), + GROUP(pwm_b_x, 2, 3), + /* bank Y */ GROUP(uart_tx_c, 1, 19), GROUP(uart_rx_c, 1, 18), @@ -537,6 +576,20 @@ static struct meson_pmx_group meson8_cbus_groups[] = { GROUP(i2c_sda_c0, 1, 15), GROUP(i2c_sck_c0, 1, 14), + GROUP(pwm_a_y, 9, 14), + + GROUP(i2s_out_ch45, 1, 10), + GROUP(i2s_out_ch23, 1, 19), + GROUP(i2s_out_ch01, 1, 6), + GROUP(i2s_in_ch01, 1, 5), + GROUP(i2s_lr_clk_in, 1, 4), + GROUP(i2s_ao_clk_in, 1, 2), + GROUP(i2s_am_clk, 1, 0), + GROUP(i2s_out_ch78, 1, 11), + + GROUP(spdif_in, 1, 8), + GROUP(spdif_out, 1, 7), + /* bank DV */ GROUP(dvin_rgb, 0, 6), GROUP(dvin_vs, 0, 9), @@ -571,6 +624,10 @@ static struct meson_pmx_group meson8_cbus_groups[] = { GROUP(vga_vs, 0, 21), GROUP(vga_hs, 0, 20), + GROUP(pwm_c_dv9, 3, 24), + GROUP(pwm_c_dv29, 3, 25), + GROUP(pwm_d, 3, 26), + /* bank H */ GROUP(hdmi_hpd, 1, 26), GROUP(hdmi_sda, 1, 25), @@ -619,6 +676,11 @@ static struct meson_pmx_group meson8_cbus_groups[] = { GROUP(i2c_sda_a2, 5, 7), GROUP(i2c_sck_a2, 5, 6), + GROUP(pwm_a_z0, 9, 16), + GROUP(pwm_a_z7, 2, 0), + GROUP(pwm_b_z, 9, 15), + GROUP(pwm_c_z, 2, 1), + /* bank BOOT */ GROUP(sd_d0_c, 6, 29), GROUP(sd_d1_c, 6, 28), @@ -689,6 +751,7 @@ static struct meson_pmx_group meson8_aobus_groups[] = { GROUP(uart_rts_ao_a, 0, 9), GROUP(remote_input, 0, 0), + GROUP(remote_output_ao, 0, 31), GROUP(i2c_slave_sck_ao, 0, 2), GROUP(i2c_slave_sda_ao, 0, 1), @@ -701,6 +764,15 @@ static struct meson_pmx_group meson8_aobus_groups[] = { GROUP(i2c_mst_sck_ao, 0, 6), GROUP(i2c_mst_sda_ao, 0, 5), + + GROUP(pwm_f_ao, 0, 19), + + GROUP(i2s_am_clk_out_ao, 0, 30), + GROUP(i2s_ao_clk_out_ao, 0, 29), + GROUP(i2s_lr_clk_out_ao, 0, 28), + GROUP(i2s_out_ch01_ao, 0, 27), + + GROUP(hdmi_cec_ao, 0, 17), }; static const char * const gpio_groups[] = { @@ -828,6 +900,12 @@ static const char * const i2c_b_groups[] = { "i2c_sda_b", "i2c_sck_b" }; +static const char * const i2s_groups[] = { + "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins", + "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins", + "i2s_am_clk_pins", "i2s_out_ch78_pins" +}; + static const char * const sd_c_groups[] = { "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", "sd_cmd_c", "sd_clk_c" @@ -849,6 +927,26 @@ static const char * const nor_groups[] = { "nor_d", "nor_q", "nor_c", "nor_cs" }; +static const char * const pwm_a_groups[] = { + "pwm_a_y", "pwm_a_z0", "pwm_a_z7" +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_x", "pwm_b_z" +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_dv9", "pwm_c_dv29", "pwm_c_z" +}; + +static const char * const pwm_d_groups[] = { + "pwm_d" +}; + +static const char * const pwm_e_groups[] = { + "pwm_e" +}; + static const char * const sd_b_groups[] = { "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b", "sd_d3_b", "sd_d2_b" @@ -858,12 +956,16 @@ static const char * const sdxc_b_groups[] = { "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" }; +static const char * const spdif_groups[] = { + "spdif_in", "spdif_out" +}; + static const char * const uart_ao_groups[] = { "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" }; static const char * const remote_groups[] = { - "remote_input" + "remote_input", "remote_output_ao" }; static const char * const i2c_slave_ao_groups[] = { @@ -878,6 +980,19 @@ static const char * const i2c_mst_ao_groups[] = { "i2c_mst_sck_ao", "i2c_mst_sda_ao" }; +static const char * const pwm_f_ao_groups[] = { + "pwm_f_ao" +}; + +static const char * const i2s_ao_groups[] = { + "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao", + "i2s_out_ch01_ao" +}; + +static const char * const hdmi_cec_ao_groups[] = { + "hdmi_cec_ao" +}; + static struct meson_pmx_func meson8_cbus_functions[] = { FUNCTION(gpio), FUNCTION(sd_a), @@ -905,6 +1020,13 @@ static struct meson_pmx_func meson8_cbus_functions[] = { FUNCTION(nor), FUNCTION(sd_b), FUNCTION(sdxc_b), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(i2s), + FUNCTION(spdif), }; static struct meson_pmx_func meson8_aobus_functions[] = { @@ -913,6 +1035,9 @@ static struct meson_pmx_func meson8_aobus_functions[] = { FUNCTION(i2c_slave_ao), FUNCTION(uart_ao_b), FUNCTION(i2c_mst_ao), + FUNCTION(pwm_f_ao), + FUNCTION(i2s_ao), + FUNCTION(hdmi_cec_ao), }; static struct meson_bank meson8_cbus_banks[] = { diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 5c96f5558310..001542f68627 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -13,7 +13,9 @@ #include <linux/gpio/driver.h> #include <linux/mfd/syscon.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/of_device.h> +#include <linux/of_irq.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> @@ -30,6 +32,11 @@ #define OUTPUT_CTL 0x20 #define SELECTION 0x30 +#define IRQ_EN 0x0 +#define IRQ_POL 0x08 +#define IRQ_STATUS 0x10 +#define IRQ_WKUP 0x18 + #define NB_FUNCS 2 #define GPIO_PER_REG 32 @@ -75,9 +82,12 @@ struct armada_37xx_pmx_func { struct armada_37xx_pinctrl { struct regmap *regmap; + void __iomem *base; const struct armada_37xx_pin_data *data; struct device *dev; struct gpio_chip gpio_chip; + struct irq_chip irq_chip; + spinlock_t irq_lock; struct pinctrl_desc pctl; struct pinctrl_dev *pctl_dev; struct armada_37xx_pin_group *groups; @@ -346,6 +356,14 @@ static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev, return armada_37xx_pmx_set_by_name(pctldev, name, grp); } +static inline void armada_37xx_irq_update_reg(unsigned int *reg, + struct irq_data *d) +{ + int offset = irqd_to_hwirq(d); + + armada_37xx_update_reg(reg, offset); +} + static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { @@ -468,6 +486,214 @@ static const struct gpio_chip armada_37xx_gpiolib_chip = { .owner = THIS_MODULE, }; +static void armada_37xx_irq_ack(struct irq_data *d) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 reg = IRQ_STATUS; + unsigned long flags; + + armada_37xx_irq_update_reg(®, d); + spin_lock_irqsave(&info->irq_lock, flags); + writel(d->mask, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); +} + +static void armada_37xx_irq_mask(struct irq_data *d) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 val, reg = IRQ_EN; + unsigned long flags; + + armada_37xx_irq_update_reg(®, d); + spin_lock_irqsave(&info->irq_lock, flags); + val = readl(info->base + reg); + writel(val & ~d->mask, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); +} + +static void armada_37xx_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 val, reg = IRQ_EN; + unsigned long flags; + + armada_37xx_irq_update_reg(®, d); + spin_lock_irqsave(&info->irq_lock, flags); + val = readl(info->base + reg); + writel(val | d->mask, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); +} + +static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 val, reg = IRQ_WKUP; + unsigned long flags; + + armada_37xx_irq_update_reg(®, d); + spin_lock_irqsave(&info->irq_lock, flags); + val = readl(info->base + reg); + if (on) + val |= d->mask; + else + val &= ~d->mask; + writel(val, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); + + return 0; +} + +static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 val, reg = IRQ_POL; + unsigned long flags; + + spin_lock_irqsave(&info->irq_lock, flags); + armada_37xx_irq_update_reg(®, d); + val = readl(info->base + reg); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val &= ~d->mask; + break; + case IRQ_TYPE_EDGE_FALLING: + val |= d->mask; + break; + default: + spin_unlock_irqrestore(&info->irq_lock, flags); + return -EINVAL; + } + writel(val, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); + + return 0; +} + + +static void armada_37xx_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct armada_37xx_pinctrl *info = gpiochip_get_data(gc); + struct irq_domain *d = gc->irqdomain; + int i; + + chained_irq_enter(chip, desc); + for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) { + u32 status; + unsigned long flags; + + spin_lock_irqsave(&info->irq_lock, flags); + status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); + /* Manage only the interrupt that was enabled */ + status &= readl_relaxed(info->base + IRQ_EN + 4 * i); + spin_unlock_irqrestore(&info->irq_lock, flags); + while (status) { + u32 hwirq = ffs(status) - 1; + u32 virq = irq_find_mapping(d, hwirq + + i * GPIO_PER_REG); + + generic_handle_irq(virq); + + /* Update status in case a new IRQ appears */ + spin_lock_irqsave(&info->irq_lock, flags); + status = readl_relaxed(info->base + + IRQ_STATUS + 4 * i); + /* Manage only the interrupt that was enabled */ + status &= readl_relaxed(info->base + IRQ_EN + 4 * i); + spin_unlock_irqrestore(&info->irq_lock, flags); + } + } + chained_irq_exit(chip, desc); +} + +static int armada_37xx_irqchip_register(struct platform_device *pdev, + struct armada_37xx_pinctrl *info) +{ + struct device_node *np = info->dev->of_node; + int nrirqs = info->data->nr_pins; + struct gpio_chip *gc = &info->gpio_chip; + struct irq_chip *irqchip = &info->irq_chip; + struct resource res; + int ret = -ENODEV, i, nr_irq_parent; + + /* Check if we have at least one gpio-controller child node */ + for_each_child_of_node(info->dev->of_node, np) { + if (of_property_read_bool(np, "gpio-controller")) { + ret = 0; + break; + } + }; + if (ret) + return ret; + + nr_irq_parent = of_irq_count(np); + spin_lock_init(&info->irq_lock); + + if (!nr_irq_parent) { + dev_err(&pdev->dev, "Invalid or no IRQ\n"); + return 0; + } + + if (of_address_to_resource(info->dev->of_node, 1, &res)) { + dev_err(info->dev, "cannot find IO resource\n"); + return -ENOENT; + } + + info->base = devm_ioremap_resource(info->dev, &res); + if (IS_ERR(info->base)) + return PTR_ERR(info->base); + + irqchip->irq_ack = armada_37xx_irq_ack; + irqchip->irq_mask = armada_37xx_irq_mask; + irqchip->irq_unmask = armada_37xx_irq_unmask; + irqchip->irq_set_wake = armada_37xx_irq_set_wake; + irqchip->irq_set_type = armada_37xx_irq_set_type; + irqchip->name = info->data->name; + + ret = gpiochip_irqchip_add(gc, irqchip, 0, + handle_edge_irq, IRQ_TYPE_NONE); + if (ret) { + dev_info(&pdev->dev, "could not add irqchip\n"); + return ret; + } + + /* + * Many interrupts are connected to the parent interrupt + * controller. But we do not take advantage of this and use + * the chained irq with all of them. + */ + for (i = 0; i < nrirqs; i++) { + struct irq_data *d = irq_get_irq_data(gc->irq_base + i); + + /* + * The mask field is a "precomputed bitmask for + * accessing the chip registers" which was introduced + * for the generic irqchip framework. As we don't use + * this framework, we can reuse this field for our own + * usage. + */ + d->mask = BIT(i % GPIO_PER_REG); + } + + for (i = 0; i < nr_irq_parent; i++) { + int irq = irq_of_parse_and_map(np, i); + + if (irq < 0) + continue; + + gpiochip_set_chained_irqchip(gc, irqchip, irq, + armada_37xx_irq_handler); + } + + return 0; +} + static int armada_37xx_gpiochip_register(struct platform_device *pdev, struct armada_37xx_pinctrl *info) { @@ -496,6 +722,9 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, ret = devm_gpiochip_add_data(&pdev->dev, gc, info); if (ret) return ret; + ret = armada_37xx_irqchip_register(pdev, info); + if (ret) + return ret; return 0; } diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index a02dba35fcf3..7fc417e4ae96 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -87,9 +87,8 @@ int pin_config_group_get(const char *dev_name, const char *pin_group, ops = pctldev->desc->confops; if (!ops || !ops->pin_config_group_get) { - dev_dbg(pctldev->dev, "cannot get configuration for pin " - "group, missing group config get function in " - "driver\n"); + dev_dbg(pctldev->dev, + "cannot get configuration for pin group, missing group config get function in driver\n"); ret = -ENOTSUPP; goto unlock; } @@ -232,7 +231,7 @@ static void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev, configs[i]); else seq_printf(s, "%08lx", configs[i]); - seq_puts(s, "\n"); + seq_putc(s, '\n'); } } @@ -244,10 +243,10 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) switch (map->type) { case PIN_MAP_TYPE_CONFIGS_PIN: - seq_printf(s, "pin "); + seq_puts(s, "pin "); break; case PIN_MAP_TYPE_CONFIGS_GROUP: - seq_printf(s, "group "); + seq_puts(s, "group "); break; default: break; @@ -319,14 +318,13 @@ static int pinconf_pins_show(struct seq_file *s, void *what) pin = pctldev->desc->pins[i].number; desc = pin_desc_get(pctldev, pin); /* Skip if we cannot search the pin */ - if (desc == NULL) + if (!desc) continue; seq_printf(s, "pin %d (%s): ", pin, desc->name); pinconf_dump_pin(pctldev, s, pin); - - seq_printf(s, "\n"); + seq_putc(s, '\n'); } mutex_unlock(&pctldev->mutex); @@ -361,8 +359,7 @@ static int pinconf_groups_show(struct seq_file *s, void *what) seq_printf(s, "%u (%s): ", selector, gname); pinconf_dump_group(pctldev, s, selector, gname); - seq_printf(s, "\n"); - + seq_putc(s, '\n'); selector++; } @@ -397,9 +394,9 @@ static const struct file_operations pinconf_groups_ops = { struct dbg_cfg { enum pinctrl_map_type map_type; - char dev_name[MAX_NAME_LEN+1]; - char state_name[MAX_NAME_LEN+1]; - char pin_name[MAX_NAME_LEN+1]; + char dev_name[MAX_NAME_LEN + 1]; + char state_name[MAX_NAME_LEN + 1]; + char pin_name[MAX_NAME_LEN + 1]; }; /* @@ -485,7 +482,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, const struct pinconf_ops *confops = NULL; struct dbg_cfg *dbg = &pinconf_dbg_conf; const struct pinctrl_map_configs *configs; - char config[MAX_NAME_LEN+1]; + char config[MAX_NAME_LEN + 1]; char buf[128]; char *b = &buf[0]; int buf_size; @@ -526,7 +523,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, /* get arg 'device_name' */ token = strsep(&b, " "); - if (token == NULL) + if (!token) return -EINVAL; if (strlen(token) >= MAX_NAME_LEN) return -EINVAL; @@ -534,7 +531,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, /* get arg 'state_name' */ token = strsep(&b, " "); - if (token == NULL) + if (!token) return -EINVAL; if (strlen(token) >= MAX_NAME_LEN) return -EINVAL; @@ -542,7 +539,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, /* get arg 'pin_name' */ token = strsep(&b, " "); - if (token == NULL) + if (!token) return -EINVAL; if (strlen(token) >= MAX_NAME_LEN) return -EINVAL; @@ -550,7 +547,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, /* get new_value of config' */ token = strsep(&b, " "); - if (token == NULL) + if (!token) return -EINVAL; if (strlen(token) >= MAX_NAME_LEN) return -EINVAL; diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 1482d132fbb8..3a390a3001f1 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -8,6 +8,10 @@ * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. + * + * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> + * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> + * */ #include <linux/err.h> diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index f141aa0430b1..5b4e1c4447fb 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2998,27 +2998,27 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rv1108-pinctrl", - .data = (void *)&rv1108_pin_ctrl }, + .data = &rv1108_pin_ctrl }, { .compatible = "rockchip,rk2928-pinctrl", - .data = (void *)&rk2928_pin_ctrl }, + .data = &rk2928_pin_ctrl }, { .compatible = "rockchip,rk3036-pinctrl", - .data = (void *)&rk3036_pin_ctrl }, + .data = &rk3036_pin_ctrl }, { .compatible = "rockchip,rk3066a-pinctrl", - .data = (void *)&rk3066a_pin_ctrl }, + .data = &rk3066a_pin_ctrl }, { .compatible = "rockchip,rk3066b-pinctrl", - .data = (void *)&rk3066b_pin_ctrl }, + .data = &rk3066b_pin_ctrl }, { .compatible = "rockchip,rk3188-pinctrl", - .data = (void *)&rk3188_pin_ctrl }, + .data = &rk3188_pin_ctrl }, { .compatible = "rockchip,rk3228-pinctrl", - .data = (void *)&rk3228_pin_ctrl }, + .data = &rk3228_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", - .data = (void *)&rk3288_pin_ctrl }, + .data = &rk3288_pin_ctrl }, { .compatible = "rockchip,rk3328-pinctrl", - .data = (void *)&rk3328_pin_ctrl }, + .data = &rk3328_pin_ctrl }, { .compatible = "rockchip,rk3368-pinctrl", - .data = (void *)&rk3368_pin_ctrl }, + .data = &rk3368_pin_ctrl }, { .compatible = "rockchip,rk3399-pinctrl", - .data = (void *)&rk3399_pin_ctrl }, + .data = &rk3399_pin_ctrl }, {}, }; diff --git a/drivers/pinctrl/zte/Kconfig b/drivers/pinctrl/zte/Kconfig new file mode 100644 index 000000000000..0d97352a24ec --- /dev/null +++ b/drivers/pinctrl/zte/Kconfig @@ -0,0 +1,13 @@ +config PINCTRL_ZX + bool + select PINMUX + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + +config PINCTRL_ZX296718 + bool "ZTE ZX296718 pinctrl driver" + depends on OF && ARCH_ZX + select PINCTRL_ZX + help + Say Y here to enable the ZX296718 pinctrl driver diff --git a/drivers/pinctrl/zte/Makefile b/drivers/pinctrl/zte/Makefile new file mode 100644 index 000000000000..c42e651d7a73 --- /dev/null +++ b/drivers/pinctrl/zte/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_PINCTRL_ZX) += pinctrl-zx.o +obj-$(CONFIG_PINCTRL_ZX296718) += pinctrl-zx296718.o diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c new file mode 100644 index 000000000000..2aca4e4b3f1c --- /dev/null +++ b/drivers/pinctrl/zte/pinctrl-zx.c @@ -0,0 +1,445 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "../pinmux.h" +#include "pinctrl-zx.h" + +#define ZX_PULL_DOWN BIT(0) +#define ZX_PULL_UP BIT(1) +#define ZX_INPUT_ENABLE BIT(3) +#define ZX_DS_SHIFT 4 +#define ZX_DS_MASK (0x7 << ZX_DS_SHIFT) +#define ZX_DS_VALUE(x) (((x) << ZX_DS_SHIFT) & ZX_DS_MASK) +#define ZX_SLEW BIT(8) + +struct zx_pinctrl { + struct pinctrl_dev *pctldev; + struct device *dev; + void __iomem *base; + void __iomem *aux_base; + spinlock_t lock; + struct zx_pinctrl_soc_info *info; +}; + +static int zx_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, u32 *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, map, + num_maps, PIN_MAP_TYPE_INVALID); +} + +static const struct pinctrl_ops zx_pinctrl_ops = { + .dt_node_to_map = zx_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, +}; + +#define NONAON_MVAL 2 + +static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, + unsigned int group_selector) +{ + struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev); + struct zx_pinctrl_soc_info *info = zpctl->info; + const struct pinctrl_pin_desc *pindesc = info->pins + group_selector; + struct zx_pin_data *data = pindesc->drv_data; + struct zx_mux_desc *mux = data->muxes; + u32 mask = (1 << data->width) - 1; + u32 offset = data->offset; + u32 bitpos = data->bitpos; + struct function_desc *func; + unsigned long flags; + u32 val, mval; + + /* Skip reserved pin */ + if (!data) + return -EINVAL; + + func = pinmux_generic_get_function(pctldev, func_selector); + if (!func) + return -EINVAL; + + while (mux->name) { + if (strcmp(mux->name, func->name) == 0) + break; + mux++; + } + + /* Found mux value to be written */ + mval = mux->muxval; + + spin_lock_irqsave(&zpctl->lock, flags); + + if (data->aon_pin) { + /* + * It's an AON pin, whose mux register offset and bit position + * can be caluculated from pin number. Each register covers 16 + * pins, and each pin occupies 2 bits. + */ + u16 aoffset = pindesc->number / 16 * 4; + u16 abitpos = (pindesc->number % 16) * 2; + + if (mval & AON_MUX_FLAG) { + /* + * This is a mux value that needs to be written into + * AON pinmux register. Write it and then we're done. + */ + val = readl(zpctl->aux_base + aoffset); + val &= ~(0x3 << abitpos); + val |= (mval & 0x3) << abitpos; + writel(val, zpctl->aux_base + aoffset); + } else { + /* + * It's a mux value that needs to be written into TOP + * pinmux register. + */ + val = readl(zpctl->base + offset); + val &= ~(mask << bitpos); + val |= (mval & mask) << bitpos; + writel(val, zpctl->base + offset); + + /* + * In this case, the AON pinmux register needs to be + * set up to select non-AON function. + */ + val = readl(zpctl->aux_base + aoffset); + val &= ~(0x3 << abitpos); + val |= NONAON_MVAL << abitpos; + writel(val, zpctl->aux_base + aoffset); + } + + } else { + /* + * This is a TOP pin, and we only need to set up TOP pinmux + * register and then we're done with it. + */ + val = readl(zpctl->base + offset); + val &= ~(mask << bitpos); + val |= (mval & mask) << bitpos; + writel(val, zpctl->base + offset); + } + + spin_unlock_irqrestore(&zpctl->lock, flags); + + return 0; +} + +static const struct pinmux_ops zx_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = zx_set_mux, +}; + +static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev); + struct zx_pinctrl_soc_info *info = zpctl->info; + const struct pinctrl_pin_desc *pindesc = info->pins + pin; + struct zx_pin_data *data = pindesc->drv_data; + enum pin_config_param param = pinconf_to_config_param(*config); + u32 val; + + /* Skip reserved pin */ + if (!data) + return -EINVAL; + + val = readl(zpctl->aux_base + data->coffset); + val = val >> data->cbitpos; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + val &= ZX_PULL_DOWN; + val = !!val; + if (val == 0) + return -EINVAL; + break; + case PIN_CONFIG_BIAS_PULL_UP: + val &= ZX_PULL_UP; + val = !!val; + if (val == 0) + return -EINVAL; + break; + case PIN_CONFIG_INPUT_ENABLE: + val &= ZX_INPUT_ENABLE; + val = !!val; + if (val == 0) + return -EINVAL; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val &= ZX_DS_MASK; + val = val >> ZX_DS_SHIFT; + break; + case PIN_CONFIG_SLEW_RATE: + val &= ZX_SLEW; + val = !!val; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, val); + + return 0; +} + +static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev); + struct zx_pinctrl_soc_info *info = zpctl->info; + const struct pinctrl_pin_desc *pindesc = info->pins + pin; + struct zx_pin_data *data = pindesc->drv_data; + enum pin_config_param param; + u32 val, arg; + int i; + + /* Skip reserved pin */ + if (!data) + return -EINVAL; + + val = readl(zpctl->aux_base + data->coffset); + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + val |= ZX_PULL_DOWN << data->cbitpos; + break; + case PIN_CONFIG_BIAS_PULL_UP: + val |= ZX_PULL_UP << data->cbitpos; + break; + case PIN_CONFIG_INPUT_ENABLE: + val |= ZX_INPUT_ENABLE << data->cbitpos; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val &= ~(ZX_DS_MASK << data->cbitpos); + val |= ZX_DS_VALUE(arg) << data->cbitpos; + break; + case PIN_CONFIG_SLEW_RATE: + if (arg) + val |= ZX_SLEW << data->cbitpos; + else + val &= ~ZX_SLEW << data->cbitpos; + break; + default: + return -ENOTSUPP; + } + } + + writel(val, zpctl->aux_base + data->coffset); + return 0; +} + +static const struct pinconf_ops zx_pinconf_ops = { + .pin_config_set = zx_pin_config_set, + .pin_config_get = zx_pin_config_get, + .is_generic = true, +}; + +static int zx_pinctrl_build_state(struct platform_device *pdev) +{ + struct zx_pinctrl *zpctl = platform_get_drvdata(pdev); + struct zx_pinctrl_soc_info *info = zpctl->info; + struct pinctrl_dev *pctldev = zpctl->pctldev; + struct function_desc *functions; + int nfunctions; + struct group_desc *groups; + int ngroups; + int i; + + /* Every single pin composes a group */ + ngroups = info->npins; + groups = devm_kzalloc(&pdev->dev, ngroups * sizeof(*groups), + GFP_KERNEL); + if (!groups) + return -ENOMEM; + + for (i = 0; i < ngroups; i++) { + const struct pinctrl_pin_desc *pindesc = info->pins + i; + struct group_desc *group = groups + i; + int id = pindesc->number; + + group->name = pindesc->name; + group->pins = &id; + radix_tree_insert(&pctldev->pin_group_tree, i, group); + } + + pctldev->num_groups = ngroups; + + /* Build function list from pin mux functions */ + functions = devm_kzalloc(&pdev->dev, info->npins * sizeof(*functions), + GFP_KERNEL); + if (!functions) + return -ENOMEM; + + nfunctions = 0; + for (i = 0; i < info->npins; i++) { + const struct pinctrl_pin_desc *pindesc = info->pins + i; + struct zx_pin_data *data = pindesc->drv_data; + struct zx_mux_desc *mux; + + /* Reserved pins do not have a drv_data at all */ + if (!data) + continue; + + /* Loop over all muxes for the pin */ + mux = data->muxes; + while (mux->name) { + struct function_desc *func = functions; + + /* Search function list for given mux */ + while (func->name) { + if (strcmp(mux->name, func->name) == 0) { + /* Function exists */ + func->num_group_names++; + break; + } + func++; + } + + if (!func->name) { + /* New function */ + func->name = mux->name; + func->num_group_names = 1; + radix_tree_insert(&pctldev->pin_function_tree, + nfunctions++, func); + } + + mux++; + } + } + + pctldev->num_functions = nfunctions; + functions = krealloc(functions, nfunctions * sizeof(*functions), + GFP_KERNEL); + + /* Find pin groups for every single function */ + for (i = 0; i < info->npins; i++) { + const struct pinctrl_pin_desc *pindesc = info->pins + i; + struct zx_pin_data *data = pindesc->drv_data; + struct zx_mux_desc *mux; + + if (!data) + continue; + + mux = data->muxes; + while (mux->name) { + struct function_desc *func; + const char **group; + int j; + + /* Find function for given mux */ + for (j = 0; j < nfunctions; j++) + if (strcmp(functions[j].name, mux->name) == 0) + break; + + func = functions + j; + if (!func->group_names) { + func->group_names = devm_kzalloc(&pdev->dev, + func->num_group_names * + sizeof(*func->group_names), + GFP_KERNEL); + if (!func->group_names) + return -ENOMEM; + } + + group = func->group_names; + while (*group) + group++; + *group = pindesc->name; + + mux++; + } + } + + return 0; +} + +int zx_pinctrl_init(struct platform_device *pdev, + struct zx_pinctrl_soc_info *info) +{ + struct pinctrl_desc *pctldesc; + struct zx_pinctrl *zpctl; + struct device_node *np; + struct resource *res; + int ret; + + zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL); + if (!zpctl) + return -ENOMEM; + + spin_lock_init(&zpctl->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + zpctl->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(zpctl->base)) + return PTR_ERR(zpctl->base); + + np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0); + if (!np) { + dev_err(&pdev->dev, "failed to find auxiliary controller\n"); + return -ENODEV; + } + + zpctl->aux_base = of_iomap(np, 0); + if (!zpctl->aux_base) + return -ENOMEM; + + zpctl->dev = &pdev->dev; + zpctl->info = info; + + pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL); + if (!pctldesc) + return -ENOMEM; + + pctldesc->name = dev_name(&pdev->dev); + pctldesc->owner = THIS_MODULE; + pctldesc->pins = info->pins; + pctldesc->npins = info->npins; + pctldesc->pctlops = &zx_pinctrl_ops; + pctldesc->pmxops = &zx_pinmux_ops; + pctldesc->confops = &zx_pinconf_ops; + + zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl); + if (IS_ERR(zpctl->pctldev)) { + ret = PTR_ERR(zpctl->pctldev); + dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, zpctl); + + ret = zx_pinctrl_build_state(pdev); + if (ret) { + dev_err(&pdev->dev, "failed to build state: %d\n", ret); + return ret; + } + + dev_info(&pdev->dev, "initialized pinctrl driver\n"); + return 0; +} diff --git a/drivers/pinctrl/zte/pinctrl-zx.h b/drivers/pinctrl/zte/pinctrl-zx.h new file mode 100644 index 000000000000..bc67e2be0503 --- /dev/null +++ b/drivers/pinctrl/zte/pinctrl-zx.h @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PINCTRL_ZX_H +#define __PINCTRL_ZX_H + +/** + * struct zx_mux_desc - hardware mux descriptor + * @name: mux function name + * @muxval: mux register bit value + */ +struct zx_mux_desc { + const char *name; + u8 muxval; +}; + +/** + * struct zx_pin_data - hardware per-pin data + * @aon_pin: whether it's an AON pin + * @offset: register offset within TOP pinmux controller + * @bitpos: bit position within TOP pinmux register + * @width: bit width within TOP pinmux register + * @coffset: pinconf register offset within AON controller + * @cbitpos: pinconf bit position within AON register + * @muxes: available mux function names and corresponding register values + * + * Unlike TOP pinmux and AON pinconf registers which are arranged pretty + * arbitrarily, AON pinmux register bits are well organized per pin id, and + * each pin occupies two bits, so that we can calculate the AON register offset + * and bit position from pin id. Thus, we only need to define TOP pinmux and + * AON pinconf register data for the pin. + */ +struct zx_pin_data { + bool aon_pin; + u16 offset; + u16 bitpos; + u16 width; + u16 coffset; + u16 cbitpos; + struct zx_mux_desc *muxes; +}; + +struct zx_pinctrl_soc_info { + const struct pinctrl_pin_desc *pins; + unsigned int npins; +}; + +#define TOP_PIN(pin, off, bp, wd, coff, cbp, ...) { \ + .number = pin, \ + .name = #pin, \ + .drv_data = &(struct zx_pin_data) { \ + .aon_pin = false, \ + .offset = off, \ + .bitpos = bp, \ + .width = wd, \ + .coffset = coff, \ + .cbitpos = cbp, \ + .muxes = (struct zx_mux_desc[]) { \ + __VA_ARGS__, { } }, \ + }, \ +} + +#define AON_PIN(pin, off, bp, wd, coff, cbp, ...) { \ + .number = pin, \ + .name = #pin, \ + .drv_data = &(struct zx_pin_data) { \ + .aon_pin = true, \ + .offset = off, \ + .bitpos = bp, \ + .width = wd, \ + .coffset = coff, \ + .cbitpos = cbp, \ + .muxes = (struct zx_mux_desc[]) { \ + __VA_ARGS__, { } }, \ + }, \ +} + +#define ZX_RESERVED(pin) PINCTRL_PIN(pin, #pin) + +#define TOP_MUX(_val, _name) { \ + .name = _name, \ + .muxval = _val, \ +} + +/* + * When the flag is set, it's a mux configuration for an AON pin that sits in + * AON register. Otherwise, it's one for AON pin but sitting in TOP register. + */ +#define AON_MUX_FLAG BIT(7) + +#define AON_MUX(_val, _name) { \ + .name = _name, \ + .muxval = _val | AON_MUX_FLAG, \ +} + +int zx_pinctrl_init(struct platform_device *pdev, + struct zx_pinctrl_soc_info *info); + +#endif /* __PINCTRL_ZX_H */ diff --git a/drivers/pinctrl/zte/pinctrl-zx296718.c b/drivers/pinctrl/zte/pinctrl-zx296718.c new file mode 100644 index 000000000000..71efec17ee7e --- /dev/null +++ b/drivers/pinctrl/zte/pinctrl-zx296718.c @@ -0,0 +1,1027 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> + +#include "pinctrl-zx.h" + +#define TOP_REG0 0x00 +#define TOP_REG1 0x04 +#define TOP_REG2 0x08 +#define TOP_REG3 0x0c +#define TOP_REG4 0x10 +#define TOP_REG5 0x14 +#define TOP_REG6 0x18 +#define TOP_REG7 0x1c +#define TOP_REG8 0x20 + +/* + * The pin numbering starts from AON pins with reserved ones included, + * so that register data like offset and bit position for AON pins can + * be calculated from pin number. + */ +enum zx296718_pin { + /* aon_pmm_reg_0 */ + I2C3_SCL = 0, + I2C3_SDA = 1, + AON_RESERVED0 = 2, + AON_RESERVED1 = 3, + SEC_EN = 4, + UART0_RXD = 5, + UART0_TXD = 6, + IR_IN = 7, + SPI0_CLK = 8, + SPI0_CS = 9, + SPI0_TXD = 10, + SPI0_RXD = 11, + KEY_COL0 = 12, + KEY_COL1 = 13, + KEY_COL2 = 14, + KEY_ROW0 = 15, + + /* aon_pmm_reg_1 */ + KEY_ROW1 = 16, + KEY_ROW2 = 17, + HDMI_SCL = 18, + HDMI_SDA = 19, + JTAG_TCK = 20, + JTAG_TRSTN = 21, + JTAG_TMS = 22, + JTAG_TDI = 23, + JTAG_TDO = 24, + I2C0_SCL = 25, + I2C0_SDA = 26, + I2C1_SCL = 27, + I2C1_SDA = 28, + AON_RESERVED2 = 29, + AON_RESERVED3 = 30, + AON_RESERVED4 = 31, + + /* aon_pmm_reg_2 */ + SPI1_CLK = 32, + SPI1_CS = 33, + SPI1_TXD = 34, + SPI1_RXD = 35, + AON_RESERVED5 = 36, + AON_RESERVED6 = 37, + AUDIO_DET = 38, + SPDIF_OUT = 39, + HDMI_CEC = 40, + HDMI_HPD = 41, + GMAC_25M_OUT = 42, + BOOT_SEL0 = 43, + BOOT_SEL1 = 44, + BOOT_SEL2 = 45, + DEEP_SLEEP_OUT_N = 46, + AON_RESERVED7 = 47, + + /* top_pmm_reg_0 */ + GMII_GTX_CLK = 48, + GMII_TX_CLK = 49, + GMII_TXD0 = 50, + GMII_TXD1 = 51, + GMII_TXD2 = 52, + GMII_TXD3 = 53, + GMII_TXD4 = 54, + GMII_TXD5 = 55, + GMII_TXD6 = 56, + GMII_TXD7 = 57, + GMII_TX_ER = 58, + GMII_TX_EN = 59, + GMII_RX_CLK = 60, + GMII_RXD0 = 61, + GMII_RXD1 = 62, + GMII_RXD2 = 63, + + /* top_pmm_reg_1 */ + GMII_RXD3 = 64, + GMII_RXD4 = 65, + GMII_RXD5 = 66, + GMII_RXD6 = 67, + GMII_RXD7 = 68, + GMII_RX_ER = 69, + GMII_RX_DV = 70, + GMII_COL = 71, + GMII_CRS = 72, + GMII_MDC = 73, + GMII_MDIO = 74, + SDIO1_CLK = 75, + SDIO1_CMD = 76, + SDIO1_DATA0 = 77, + SDIO1_DATA1 = 78, + SDIO1_DATA2 = 79, + + /* top_pmm_reg_2 */ + SDIO1_DATA3 = 80, + SDIO1_CD = 81, + SDIO1_WP = 82, + USIM1_CD = 83, + USIM1_CLK = 84, + USIM1_RST = 85, + + /* top_pmm_reg_3 */ + USIM1_DATA = 86, + SDIO0_CLK = 87, + SDIO0_CMD = 88, + SDIO0_DATA0 = 89, + SDIO0_DATA1 = 90, + SDIO0_DATA2 = 91, + SDIO0_DATA3 = 92, + SDIO0_CD = 93, + SDIO0_WP = 94, + + /* top_pmm_reg_4 */ + TSI0_DATA0 = 95, + SPINOR_CLK = 96, + TSI2_DATA = 97, + TSI2_CLK = 98, + TSI2_SYNC = 99, + TSI2_VALID = 100, + SPINOR_CS = 101, + SPINOR_DQ0 = 102, + SPINOR_DQ1 = 103, + SPINOR_DQ2 = 104, + SPINOR_DQ3 = 105, + VGA_HS = 106, + VGA_VS = 107, + TSI3_DATA = 108, + + /* top_pmm_reg_5 */ + TSI3_CLK = 109, + TSI3_SYNC = 110, + TSI3_VALID = 111, + I2S1_WS = 112, + I2S1_BCLK = 113, + I2S1_MCLK = 114, + I2S1_DIN0 = 115, + I2S1_DOUT0 = 116, + SPI3_CLK = 117, + SPI3_CS = 118, + SPI3_TXD = 119, + NAND_LDO_MS18_SEL = 120, + + /* top_pmm_reg_6 */ + SPI3_RXD = 121, + I2S0_MCLK = 122, + I2S0_BCLK = 123, + I2S0_WS = 124, + I2S0_DIN0 = 125, + I2S0_DOUT0 = 126, + I2C5_SCL = 127, + I2C5_SDA = 128, + SPI2_CLK = 129, + SPI2_CS = 130, + SPI2_TXD = 131, + + /* top_pmm_reg_7 */ + SPI2_RXD = 132, + NAND_WP_N = 133, + NAND_PAGE_SIZE0 = 134, + NAND_PAGE_SIZE1 = 135, + NAND_ADDR_CYCLE = 136, + NAND_RB0 = 137, + NAND_RB1 = 138, + NAND_RB2 = 139, + NAND_RB3 = 140, + + /* top_pmm_reg_8 */ + GMAC_125M_IN = 141, + GMAC_50M_OUT = 142, + SPINOR_SSCLK_LOOPBACK = 143, + SPINOR_SDIO1CLK_LOOPBACK = 144, +}; + +static const struct pinctrl_pin_desc zx296718_pins[] = { + /* aon_pmm_reg_0 */ + AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0, + AON_MUX(0x0, "ANMI"), /* anmi */ + AON_MUX(0x1, "AGPIO"), /* agpio29 */ + AON_MUX(0x2, "nonAON"), /* pin0 */ + AON_MUX(0x3, "EXT_INT"), /* int4 */ + TOP_MUX(0x0, "I2C3"), /* scl */ + TOP_MUX(0x1, "SPI2"), /* txd */ + TOP_MUX(0x2, "I2S1")), /* din0 */ + AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9, + AON_MUX(0x0, "WD"), /* rst_b */ + AON_MUX(0x1, "AGPIO"), /* agpio30 */ + AON_MUX(0x2, "nonAON"), /* pin1 */ + AON_MUX(0x3, "EXT_INT"), /* int5 */ + TOP_MUX(0x0, "I2C3"), /* sda */ + TOP_MUX(0x1, "SPI2"), /* rxd */ + TOP_MUX(0x2, "I2S0")), /* mclk */ + ZX_RESERVED(AON_RESERVED0), + ZX_RESERVED(AON_RESERVED1), + AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0, + AON_MUX(0x0, "SEC"), /* en */ + AON_MUX(0x1, "AGPIO"), /* agpio28 */ + AON_MUX(0x2, "nonAON"), /* pin3 */ + AON_MUX(0x3, "EXT_INT"), /* int7 */ + TOP_MUX(0x0, "I2C2"), /* sda */ + TOP_MUX(0x1, "SPI2")), /* cs */ + AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9, + AON_MUX(0x0, "UART0"), /* rxd */ + AON_MUX(0x1, "AGPIO"), /* agpio20 */ + AON_MUX(0x2, "nonAON")), /* pin34 */ + AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18, + AON_MUX(0x0, "UART0"), /* txd */ + AON_MUX(0x1, "AGPIO"), /* agpio21 */ + AON_MUX(0x2, "nonAON")), /* pin32 */ + AON_PIN(IR_IN, 0, 0, 0, 0x64, 0, + AON_MUX(0x0, "IR"), /* in */ + AON_MUX(0x1, "AGPIO"), /* agpio0 */ + AON_MUX(0x2, "nonAON")), /* pin27 */ + AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9, + AON_MUX(0x0, "EXT_INT"), /* int0 */ + AON_MUX(0x1, "AGPIO"), /* agpio23 */ + AON_MUX(0x2, "nonAON"), /* pin5 */ + AON_MUX(0x3, "PCU"), /* test6 */ + TOP_MUX(0x0, "SPI0"), /* clk */ + TOP_MUX(0x1, "ISP")), /* flash_trig */ + AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18, + AON_MUX(0x0, "EXT_INT"), /* int1 */ + AON_MUX(0x1, "AGPIO"), /* agpio24 */ + AON_MUX(0x2, "nonAON"), /* pin6 */ + AON_MUX(0x3, "PCU"), /* test0 */ + TOP_MUX(0x0, "SPI0"), /* cs */ + TOP_MUX(0x1, "ISP")), /* prelight_trig */ + AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0, + AON_MUX(0x0, "EXT_INT"), /* int2 */ + AON_MUX(0x1, "AGPIO"), /* agpio25 */ + AON_MUX(0x2, "nonAON"), /* pin7 */ + AON_MUX(0x3, "PCU"), /* test1 */ + TOP_MUX(0x0, "SPI0"), /* txd */ + TOP_MUX(0x1, "ISP")), /* shutter_trig */ + AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9, + AON_MUX(0x0, "EXT_INT"), /* int3 */ + AON_MUX(0x1, "AGPIO"), /* agpio26 */ + AON_MUX(0x2, "nonAON"), /* pin8 */ + AON_MUX(0x3, "PCU"), /* test2 */ + TOP_MUX(0x0, "SPI0"), /* rxd */ + TOP_MUX(0x1, "ISP")), /* shutter_open */ + AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18, + AON_MUX(0x0, "KEY"), /* col0 */ + AON_MUX(0x1, "AGPIO"), /* agpio5 */ + AON_MUX(0x2, "nonAON"), /* pin9 */ + AON_MUX(0x3, "PCU"), /* test3 */ + TOP_MUX(0x0, "UART3"), /* rxd */ + TOP_MUX(0x1, "I2S0")), /* din1 */ + AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0, + AON_MUX(0x0, "KEY"), /* col1 */ + AON_MUX(0x1, "AGPIO"), /* agpio6 */ + AON_MUX(0x2, "nonAON"), /* pin10 */ + TOP_MUX(0x0, "UART3"), /* txd */ + TOP_MUX(0x1, "I2S0"), /* din2 */ + TOP_MUX(0x2, "VGA")), /* scl */ + AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9, + AON_MUX(0x0, "KEY"), /* col2 */ + AON_MUX(0x1, "AGPIO"), /* agpio7 */ + AON_MUX(0x2, "nonAON"), /* pin11 */ + TOP_MUX(0x0, "PWM"), /* out1 */ + TOP_MUX(0x1, "I2S0"), /* din3 */ + TOP_MUX(0x2, "VGA")), /* sda */ + AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18, + AON_MUX(0x0, "KEY"), /* row0 */ + AON_MUX(0x1, "AGPIO"), /* agpio8 */ + AON_MUX(0x2, "nonAON"), /* pin33 */ + AON_MUX(0x3, "WD")), /* rst_b */ + + /* aon_pmm_reg_1 */ + AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0, + AON_MUX(0x0, "KEY"), /* row1 */ + AON_MUX(0x1, "AGPIO"), /* agpio9 */ + AON_MUX(0x2, "nonAON"), /* pin12 */ + TOP_MUX(0x0, "LCD"), /* port0 lcd_te */ + TOP_MUX(0x1, "I2S0"), /* dout2 */ + TOP_MUX(0x2, "PWM"), /* out2 */ + TOP_MUX(0x3, "VGA")), /* hs1 */ + AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9, + AON_MUX(0x0, "KEY"), /* row2 */ + AON_MUX(0x1, "AGPIO"), /* agpio10 */ + AON_MUX(0x2, "nonAON"), /* pin13 */ + TOP_MUX(0x0, "LCD"), /* port1 lcd_te */ + TOP_MUX(0x1, "I2S0"), /* dout3 */ + TOP_MUX(0x2, "PWM"), /* out3 */ + TOP_MUX(0x3, "VGA")), /* vs1 */ + AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18, + AON_MUX(0x0, "PCU"), /* test7 */ + AON_MUX(0x1, "AGPIO"), /* agpio3 */ + AON_MUX(0x2, "nonAON"), /* pin14 */ + TOP_MUX(0x0, "HDMI"), /* scl */ + TOP_MUX(0x1, "UART3")), /* rxd */ + AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0, + AON_MUX(0x0, "PCU"), /* test8 */ + AON_MUX(0x1, "AGPIO"), /* agpio4 */ + AON_MUX(0x2, "nonAON"), /* pin15 */ + TOP_MUX(0x0, "HDMI"), /* sda */ + TOP_MUX(0x1, "UART3")), /* txd */ + AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18, + AON_MUX(0x0, "JTAG"), /* tck */ + AON_MUX(0x1, "AGPIO"), /* agpio11 */ + AON_MUX(0x2, "nonAON"), /* pin22 */ + AON_MUX(0x3, "EXT_INT"), /* int4 */ + TOP_MUX(0x0, "SPI4"), /* clk */ + TOP_MUX(0x1, "UART1")), /* rxd */ + AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0, + AON_MUX(0x0, "JTAG"), /* trstn */ + AON_MUX(0x1, "AGPIO"), /* agpio12 */ + AON_MUX(0x2, "nonAON"), /* pin23 */ + AON_MUX(0x3, "EXT_INT"), /* int5 */ + TOP_MUX(0x0, "SPI4"), /* cs */ + TOP_MUX(0x1, "UART1")), /* txd */ + AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9, + AON_MUX(0x0, "JTAG"), /* tms */ + AON_MUX(0x1, "AGPIO"), /* agpio13 */ + AON_MUX(0x2, "nonAON"), /* pin24 */ + AON_MUX(0x3, "EXT_INT"), /* int6 */ + TOP_MUX(0x0, "SPI4"), /* txd */ + TOP_MUX(0x1, "UART2")), /* rxd */ + AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18, + AON_MUX(0x0, "JTAG"), /* tdi */ + AON_MUX(0x1, "AGPIO"), /* agpio14 */ + AON_MUX(0x2, "nonAON"), /* pin25 */ + AON_MUX(0x3, "EXT_INT"), /* int7 */ + TOP_MUX(0x0, "SPI4"), /* rxd */ + TOP_MUX(0x1, "UART2")), /* txd */ + AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0, + AON_MUX(0x0, "JTAG"), /* tdo */ + AON_MUX(0x1, "AGPIO"), /* agpio15 */ + AON_MUX(0x2, "nonAON")), /* pin26 */ + AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9, + AON_MUX(0x0, "I2C0"), /* scl */ + AON_MUX(0x1, "AGPIO"), /* agpio16 */ + AON_MUX(0x2, "nonAON")), /* pin28 */ + AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18, + AON_MUX(0x0, "I2C0"), /* sda */ + AON_MUX(0x1, "AGPIO"), /* agpio17 */ + AON_MUX(0x2, "nonAON")), /* pin29 */ + AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0, + AON_MUX(0x0, "I2C1"), /* scl */ + AON_MUX(0x1, "AGPIO"), /* agpio18 */ + AON_MUX(0x2, "nonAON"), /* pin30 */ + TOP_MUX(0x0, "LCD")), /* port0 lcd_te */ + AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9, + AON_MUX(0x0, "I2C1"), /* sda */ + AON_MUX(0x1, "AGPIO"), /* agpio19 */ + AON_MUX(0x2, "nonAON"), /* pin31 */ + TOP_MUX(0x0, "LCD")), /* port1 lcd_te */ + ZX_RESERVED(AON_RESERVED2), + ZX_RESERVED(AON_RESERVED3), + ZX_RESERVED(AON_RESERVED4), + + /* aon_pmm_reg_2 */ + AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9, + AON_MUX(0x0, "EXT_INT"), /* int0 */ + AON_MUX(0x1, "PCU"), /* test12 */ + AON_MUX(0x2, "nonAON"), /* pin39 */ + TOP_MUX(0x0, "SPI1"), /* clk */ + TOP_MUX(0x1, "PCM"), /* clk */ + TOP_MUX(0x2, "BGPIO"), /* gpio35 */ + TOP_MUX(0x3, "I2C4"), /* scl */ + TOP_MUX(0x4, "I2S1"), /* mclk */ + TOP_MUX(0x5, "ISP")), /* flash_trig */ + AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18, + AON_MUX(0x0, "EXT_INT"), /* int1 */ + AON_MUX(0x1, "PCU"), /* test13 */ + AON_MUX(0x2, "nonAON"), /* pin40 */ + TOP_MUX(0x0, "SPI1"), /* cs */ + TOP_MUX(0x1, "PCM"), /* fs */ + TOP_MUX(0x2, "BGPIO"), /* gpio36 */ + TOP_MUX(0x3, "I2C4"), /* sda */ + TOP_MUX(0x4, "I2S1"), /* bclk */ + TOP_MUX(0x5, "ISP")), /* prelight_trig */ + AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0, + AON_MUX(0x0, "EXT_INT"), /* int2 */ + AON_MUX(0x1, "PCU"), /* test14 */ + AON_MUX(0x2, "nonAON"), /* pin41 */ + TOP_MUX(0x0, "SPI1"), /* txd */ + TOP_MUX(0x1, "PCM"), /* txd */ + TOP_MUX(0x2, "BGPIO"), /* gpio37 */ + TOP_MUX(0x3, "UART5"), /* rxd */ + TOP_MUX(0x4, "I2S1"), /* ws */ + TOP_MUX(0x5, "ISP")), /* shutter_trig */ + AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9, + AON_MUX(0x0, "EXT_INT"), /* int3 */ + AON_MUX(0x1, "PCU"), /* test15 */ + AON_MUX(0x2, "nonAON"), /* pin42 */ + TOP_MUX(0x0, "SPI1"), /* rxd */ + TOP_MUX(0x1, "PCM"), /* rxd */ + TOP_MUX(0x2, "BGPIO"), /* gpio38 */ + TOP_MUX(0x3, "UART5"), /* txd */ + TOP_MUX(0x4, "I2S1"), /* dout0 */ + TOP_MUX(0x5, "ISP")), /* shutter_open */ + ZX_RESERVED(AON_RESERVED5), + ZX_RESERVED(AON_RESERVED6), + AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18, + AON_MUX(0x0, "PCU"), /* test4 */ + AON_MUX(0x1, "AGPIO"), /* agpio27 */ + AON_MUX(0x2, "nonAON"), /* pin2 */ + AON_MUX(0x3, "EXT_INT"), /* int16 */ + TOP_MUX(0x0, "AUDIO"), /* detect */ + TOP_MUX(0x1, "I2C2"), /* scl */ + TOP_MUX(0x2, "SPI2")), /* clk */ + AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9, + AON_MUX(0x0, "PCU"), /* test5 */ + AON_MUX(0x1, "AGPIO"), /* agpio22 */ + AON_MUX(0x2, "nonAON"), /* pin4 */ + TOP_MUX(0x0, "SPDIF"), /* out */ + TOP_MUX(0x1, "PWM"), /* out0 */ + TOP_MUX(0x2, "ISP")), /* fl_trig */ + AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9, + AON_MUX(0x0, "PCU"), /* test9 */ + AON_MUX(0x1, "AGPIO"), /* agpio1 */ + AON_MUX(0x2, "nonAON")), /* pin16 */ + AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18, + AON_MUX(0x0, "PCU"), /* test10 */ + AON_MUX(0x1, "AGPIO"), /* agpio2 */ + AON_MUX(0x2, "nonAON")), /* pin17 */ + AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0, + AON_MUX(0x0, "PCU"), /* test11 */ + AON_MUX(0x1, "AGPIO"), /* agpio31 */ + AON_MUX(0x2, "nonAON")), /* pin43 */ + AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9, + AON_MUX(0x0, "BOOT"), /* sel0 */ + AON_MUX(0x1, "AGPIO"), /* agpio18 */ + AON_MUX(0x2, "nonAON")), /* pin18 */ + AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18, + AON_MUX(0x0, "BOOT"), /* sel1 */ + AON_MUX(0x1, "AGPIO"), /* agpio19 */ + AON_MUX(0x2, "nonAON")), /* pin19 */ + AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0, + AON_MUX(0x0, "BOOT"), /* sel2 */ + AON_MUX(0x1, "AGPIO"), /* agpio20 */ + AON_MUX(0x2, "nonAON")), /* pin20 */ + AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9, + AON_MUX(0x0, "DEEPSLP"), /* deep sleep out_n */ + AON_MUX(0x1, "AGPIO"), /* agpio21 */ + AON_MUX(0x2, "nonAON")), /* pin21 */ + ZX_RESERVED(AON_RESERVED7), + + /* top_pmm_reg_0 */ + TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0, + TOP_MUX(0x0, "GMII"), /* gtx_clk */ + TOP_MUX(0x1, "DVI0"), /* clk */ + TOP_MUX(0x2, "BGPIO")), /* gpio0 */ + TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9, + TOP_MUX(0x0, "GMII"), /* tx_clk */ + TOP_MUX(0x1, "DVI0"), /* vs */ + TOP_MUX(0x2, "BGPIO")), /* gpio1 */ + TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18, + TOP_MUX(0x0, "GMII"), /* txd0 */ + TOP_MUX(0x1, "DVI0"), /* hs */ + TOP_MUX(0x2, "BGPIO")), /* gpio2 */ + TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0, + TOP_MUX(0x0, "GMII"), /* txd1 */ + TOP_MUX(0x1, "DVI0"), /* d0 */ + TOP_MUX(0x2, "BGPIO")), /* gpio3 */ + TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9, + TOP_MUX(0x0, "GMII"), /* txd2 */ + TOP_MUX(0x1, "DVI0"), /* d1 */ + TOP_MUX(0x2, "BGPIO")), /* gpio4 */ + TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18, + TOP_MUX(0x0, "GMII"), /* txd3 */ + TOP_MUX(0x1, "DVI0"), /* d2 */ + TOP_MUX(0x2, "BGPIO")), /* gpio5 */ + TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0, + TOP_MUX(0x0, "GMII"), /* txd4 */ + TOP_MUX(0x1, "DVI0"), /* d3 */ + TOP_MUX(0x2, "BGPIO")), /* gpio6 */ + TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9, + TOP_MUX(0x0, "GMII"), /* txd5 */ + TOP_MUX(0x1, "DVI0"), /* d4 */ + TOP_MUX(0x2, "BGPIO")), /* gpio7 */ + TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18, + TOP_MUX(0x0, "GMII"), /* txd6 */ + TOP_MUX(0x1, "DVI0"), /* d5 */ + TOP_MUX(0x2, "BGPIO")), /* gpio8 */ + TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0, + TOP_MUX(0x0, "GMII"), /* txd7 */ + TOP_MUX(0x1, "DVI0"), /* d6 */ + TOP_MUX(0x2, "BGPIO")), /* gpio9 */ + TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9, + TOP_MUX(0x0, "GMII"), /* tx_er */ + TOP_MUX(0x1, "DVI0"), /* d7 */ + TOP_MUX(0x2, "BGPIO")), /* gpio10 */ + TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18, + TOP_MUX(0x0, "GMII"), /* tx_en */ + TOP_MUX(0x1, "DVI0"), /* d8 */ + TOP_MUX(0x3, "BGPIO")), /* gpio11 */ + TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0, + TOP_MUX(0x0, "GMII"), /* rx_clk */ + TOP_MUX(0x1, "DVI0"), /* d9 */ + TOP_MUX(0x3, "BGPIO")), /* gpio12 */ + TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9, + TOP_MUX(0x0, "GMII"), /* rxd0 */ + TOP_MUX(0x1, "DVI0"), /* d10 */ + TOP_MUX(0x3, "BGPIO")), /* gpio13 */ + TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18, + TOP_MUX(0x0, "GMII"), /* rxd1 */ + TOP_MUX(0x1, "DVI0"), /* d11 */ + TOP_MUX(0x2, "BGPIO")), /* gpio14 */ + TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0, + TOP_MUX(0x0, "GMII"), /* rxd2 */ + TOP_MUX(0x1, "DVI1"), /* clk */ + TOP_MUX(0x2, "BGPIO")), /* gpio15 */ + + /* top_pmm_reg_1 */ + TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9, + TOP_MUX(0x0, "GMII"), /* rxd3 */ + TOP_MUX(0x1, "DVI1"), /* hs */ + TOP_MUX(0x2, "BGPIO")), /* gpio16 */ + TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18, + TOP_MUX(0x0, "GMII"), /* rxd4 */ + TOP_MUX(0x1, "DVI1"), /* vs */ + TOP_MUX(0x2, "BGPIO")), /* gpio17 */ + TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0, + TOP_MUX(0x0, "GMII"), /* rxd5 */ + TOP_MUX(0x1, "DVI1"), /* d0 */ + TOP_MUX(0x2, "BGPIO"), /* gpio18 */ + TOP_MUX(0x3, "TSI0")), /* dat0 */ + TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9, + TOP_MUX(0x0, "GMII"), /* rxd6 */ + TOP_MUX(0x1, "DVI1"), /* d1 */ + TOP_MUX(0x2, "BGPIO"), /* gpio19 */ + TOP_MUX(0x3, "TSI0")), /* clk */ + TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18, + TOP_MUX(0x0, "GMII"), /* rxd7 */ + TOP_MUX(0x1, "DVI1"), /* d2 */ + TOP_MUX(0x2, "BGPIO"), /* gpio20 */ + TOP_MUX(0x3, "TSI0")), /* sync */ + TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0, + TOP_MUX(0x0, "GMII"), /* rx_er */ + TOP_MUX(0x1, "DVI1"), /* d3 */ + TOP_MUX(0x2, "BGPIO"), /* gpio21 */ + TOP_MUX(0x3, "TSI0")), /* valid */ + TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9, + TOP_MUX(0x0, "GMII"), /* rx_dv */ + TOP_MUX(0x1, "DVI1"), /* d4 */ + TOP_MUX(0x2, "BGPIO"), /* gpio22 */ + TOP_MUX(0x3, "TSI1")), /* dat0 */ + TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18, + TOP_MUX(0x0, "GMII"), /* col */ + TOP_MUX(0x1, "DVI1"), /* d5 */ + TOP_MUX(0x2, "BGPIO"), /* gpio23 */ + TOP_MUX(0x3, "TSI1")), /* clk */ + TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0, + TOP_MUX(0x0, "GMII"), /* crs */ + TOP_MUX(0x1, "DVI1"), /* d6 */ + TOP_MUX(0x2, "BGPIO"), /* gpio24 */ + TOP_MUX(0x3, "TSI1")), /* sync */ + TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9, + TOP_MUX(0x0, "GMII"), /* mdc */ + TOP_MUX(0x1, "DVI1"), /* d7 */ + TOP_MUX(0x2, "BGPIO"), /* gpio25 */ + TOP_MUX(0x3, "TSI1")), /* valid */ + TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18, + TOP_MUX(0x0, "GMII"), /* mdio */ + TOP_MUX(0x2, "BGPIO")), /* gpio26 */ + TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18, + TOP_MUX(0x0, "SDIO1"), /* clk */ + TOP_MUX(0x1, "USIM0"), /* clk */ + TOP_MUX(0x2, "BGPIO"), /* gpio27 */ + TOP_MUX(0x3, "SPINOR")), /* clk */ + TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0, + TOP_MUX(0x0, "SDIO1"), /* cmd */ + TOP_MUX(0x1, "USIM0"), /* cd */ + TOP_MUX(0x2, "BGPIO"), /* gpio28 */ + TOP_MUX(0x3, "SPINOR")), /* cs */ + TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9, + TOP_MUX(0x0, "SDIO1"), /* dat0 */ + TOP_MUX(0x1, "USIM0"), /* rst */ + TOP_MUX(0x2, "BGPIO"), /* gpio29 */ + TOP_MUX(0x3, "SPINOR")), /* dq0 */ + TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18, + TOP_MUX(0x0, "SDIO1"), /* dat1 */ + TOP_MUX(0x1, "USIM0"), /* data */ + TOP_MUX(0x2, "BGPIO"), /* gpio30 */ + TOP_MUX(0x3, "SPINOR")), /* dq1 */ + TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0, + TOP_MUX(0x0, "SDIO1"), /* dat2 */ + TOP_MUX(0x1, "BGPIO"), /* gpio31 */ + TOP_MUX(0x2, "SPINOR")), /* dq2 */ + + /* top_pmm_reg_2 */ + TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9, + TOP_MUX(0x0, "SDIO1"), /* dat3 */ + TOP_MUX(0x1, "BGPIO"), /* gpio32 */ + TOP_MUX(0x2, "SPINOR")), /* dq3 */ + TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18, + TOP_MUX(0x0, "SDIO1"), /* cd */ + TOP_MUX(0x1, "BGPIO"), /* gpio33 */ + TOP_MUX(0x2, "ISP")), /* fl_trig */ + TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0, + TOP_MUX(0x0, "SDIO1"), /* wp */ + TOP_MUX(0x1, "BGPIO"), /* gpio34 */ + TOP_MUX(0x2, "ISP")), /* ref_clk */ + TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18, + TOP_MUX(0x0, "USIM1"), /* cd */ + TOP_MUX(0x1, "UART4"), /* rxd */ + TOP_MUX(0x2, "BGPIO"), /* gpio39 */ + TOP_MUX(0x3, "SPI3"), /* clk */ + TOP_MUX(0x4, "I2S0"), /* bclk */ + TOP_MUX(0x5, "B_DVI0")), /* d8 */ + TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18, + TOP_MUX(0x0, "USIM1"), /* clk */ + TOP_MUX(0x1, "UART4"), /* txd */ + TOP_MUX(0x2, "BGPIO"), /* gpio40 */ + TOP_MUX(0x3, "SPI3"), /* cs */ + TOP_MUX(0x4, "I2S0"), /* ws */ + TOP_MUX(0x5, "B_DVI0")), /* d9 */ + TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0, + TOP_MUX(0x0, "USIM1"), /* rst */ + TOP_MUX(0x1, "UART4"), /* cts */ + TOP_MUX(0x2, "BGPIO"), /* gpio41 */ + TOP_MUX(0x3, "SPI3"), /* txd */ + TOP_MUX(0x4, "I2S0"), /* dout0 */ + TOP_MUX(0x5, "B_DVI0")), /* d10 */ + + /* top_pmm_reg_3 */ + TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9, + TOP_MUX(0x0, "USIM1"), /* dat */ + TOP_MUX(0x1, "UART4"), /* rst */ + TOP_MUX(0x2, "BGPIO"), /* gpio42 */ + TOP_MUX(0x3, "SPI3"), /* rxd */ + TOP_MUX(0x4, "I2S0"), /* din0 */ + TOP_MUX(0x5, "B_DVI0")), /* d11 */ + TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0, + TOP_MUX(0x0, "SDIO0"), /* clk */ + TOP_MUX(0x1, "GPIO")), /* gpio43 */ + TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9, + TOP_MUX(0x0, "SDIO0"), /* cmd */ + TOP_MUX(0x1, "GPIO")), /* gpio44 */ + TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18, + TOP_MUX(0x0, "SDIO0"), /* dat0 */ + TOP_MUX(0x1, "GPIO")), /* gpio45 */ + TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0, + TOP_MUX(0x0, "SDIO0"), /* dat1 */ + TOP_MUX(0x1, "GPIO")), /* gpio46 */ + TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9, + TOP_MUX(0x0, "SDIO0"), /* dat2 */ + TOP_MUX(0x1, "GPIO")), /* gpio47 */ + TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18, + TOP_MUX(0x0, "SDIO0"), /* dat3 */ + TOP_MUX(0x1, "GPIO")), /* gpio48 */ + TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0, + TOP_MUX(0x0, "SDIO0"), /* cd */ + TOP_MUX(0x1, "GPIO")), /* gpio49 */ + TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9, + TOP_MUX(0x0, "SDIO0"), /* wp */ + TOP_MUX(0x1, "GPIO")), /* gpio50 */ + + /* top_pmm_reg_4 */ + TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18, + TOP_MUX(0x0, "TSI0"), /* dat0 */ + TOP_MUX(0x1, "LCD"), /* clk */ + TOP_MUX(0x2, "BGPIO")), /* gpio51 */ + TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18, + TOP_MUX(0x0, "SPINOR"), /* clk */ + TOP_MUX(0x1, "TSI0"), /* dat1 */ + TOP_MUX(0x2, "LCD"), /* dat0 */ + TOP_MUX(0x3, "BGPIO")), /* gpio52 */ + TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0, + TOP_MUX(0x0, "TSI2"), /* dat */ + TOP_MUX(0x1, "TSI0"), /* dat2 */ + TOP_MUX(0x2, "LCD"), /* dat1 */ + TOP_MUX(0x3, "BGPIO")), /* gpio53 */ + TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9, + TOP_MUX(0x0, "TSI2"), /* clk */ + TOP_MUX(0x1, "TSI0"), /* dat3 */ + TOP_MUX(0x2, "LCD"), /* dat2 */ + TOP_MUX(0x3, "BGPIO")), /* gpio54 */ + TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18, + TOP_MUX(0x0, "TSI2"), /* sync */ + TOP_MUX(0x1, "TSI0"), /* dat4 */ + TOP_MUX(0x2, "LCD"), /* dat3 */ + TOP_MUX(0x3, "BGPIO")), /* gpio55 */ + TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0, + TOP_MUX(0x0, "TSI2"), /* valid */ + TOP_MUX(0x1, "TSI0"), /* dat5 */ + TOP_MUX(0x2, "LCD"), /* dat4 */ + TOP_MUX(0x3, "BGPIO")), /* gpio56 */ + TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9, + TOP_MUX(0x0, "SPINOR"), /* cs */ + TOP_MUX(0x1, "TSI0"), /* dat6 */ + TOP_MUX(0x2, "LCD"), /* dat5 */ + TOP_MUX(0x3, "BGPIO")), /* gpio57 */ + TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18, + TOP_MUX(0x0, "SPINOR"), /* dq0 */ + TOP_MUX(0x1, "TSI0"), /* dat7 */ + TOP_MUX(0x2, "LCD"), /* dat6 */ + TOP_MUX(0x3, "BGPIO")), /* gpio58 */ + TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0, + TOP_MUX(0x0, "SPINOR"), /* dq1 */ + TOP_MUX(0x1, "TSI0"), /* clk */ + TOP_MUX(0x2, "LCD"), /* dat7 */ + TOP_MUX(0x3, "BGPIO")), /* gpio59 */ + TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9, + TOP_MUX(0x0, "SPINOR"), /* dq2 */ + TOP_MUX(0x1, "TSI0"), /* sync */ + TOP_MUX(0x2, "LCD"), /* dat8 */ + TOP_MUX(0x3, "BGPIO")), /* gpio60 */ + TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18, + TOP_MUX(0x0, "SPINOR"), /* dq3 */ + TOP_MUX(0x1, "TSI0"), /* valid */ + TOP_MUX(0x2, "LCD"), /* dat9 */ + TOP_MUX(0x3, "BGPIO")), /* gpio61 */ + TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0, + TOP_MUX(0x0, "VGA"), /* hs */ + TOP_MUX(0x1, "TSI1"), /* dat0 */ + TOP_MUX(0x2, "LCD"), /* dat10 */ + TOP_MUX(0x3, "BGPIO"), /* gpio62 */ + TOP_MUX(0x4, "I2S1"), /* din1 */ + TOP_MUX(0x5, "B_DVI0")), /* clk */ + TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9, + TOP_MUX(0x0, "VGA"), /* vs0 */ + TOP_MUX(0x1, "TSI1"), /* dat1 */ + TOP_MUX(0x2, "LCD"), /* dat11 */ + TOP_MUX(0x3, "BGPIO"), /* gpio63 */ + TOP_MUX(0x4, "I2S1"), /* din2 */ + TOP_MUX(0x5, "B_DVI0")), /* vs */ + TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18, + TOP_MUX(0x0, "TSI3"), /* dat */ + TOP_MUX(0x1, "TSI1"), /* dat2 */ + TOP_MUX(0x2, "LCD"), /* dat12 */ + TOP_MUX(0x3, "BGPIO"), /* gpio64 */ + TOP_MUX(0x4, "I2S1"), /* din3 */ + TOP_MUX(0x5, "B_DVI0")), /* hs */ + + /* top_pmm_reg_5 */ + TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0, + TOP_MUX(0x0, "TSI3"), /* clk */ + TOP_MUX(0x1, "TSI1"), /* dat3 */ + TOP_MUX(0x2, "LCD"), /* dat13 */ + TOP_MUX(0x3, "BGPIO"), /* gpio65 */ + TOP_MUX(0x4, "I2S1"), /* dout1 */ + TOP_MUX(0x5, "B_DVI0")), /* d0 */ + TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9, + TOP_MUX(0x0, "TSI3"), /* sync */ + TOP_MUX(0x1, "TSI1"), /* dat4 */ + TOP_MUX(0x2, "LCD"), /* dat14 */ + TOP_MUX(0x3, "BGPIO"), /* gpio66 */ + TOP_MUX(0x4, "I2S1"), /* dout2 */ + TOP_MUX(0x5, "B_DVI0")), /* d1 */ + TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18, + TOP_MUX(0x0, "TSI3"), /* valid */ + TOP_MUX(0x1, "TSI1"), /* dat5 */ + TOP_MUX(0x2, "LCD"), /* dat15 */ + TOP_MUX(0x3, "BGPIO"), /* gpio67 */ + TOP_MUX(0x4, "I2S1"), /* dout3 */ + TOP_MUX(0x5, "B_DVI0")), /* d2 */ + TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0, + TOP_MUX(0x0, "I2S1"), /* ws */ + TOP_MUX(0x1, "TSI1"), /* dat6 */ + TOP_MUX(0x2, "LCD"), /* dat16 */ + TOP_MUX(0x3, "BGPIO"), /* gpio68 */ + TOP_MUX(0x4, "VGA"), /* scl */ + TOP_MUX(0x5, "B_DVI0")), /* d3 */ + TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9, + TOP_MUX(0x0, "I2S1"), /* bclk */ + TOP_MUX(0x1, "TSI1"), /* dat7 */ + TOP_MUX(0x2, "LCD"), /* dat17 */ + TOP_MUX(0x3, "BGPIO"), /* gpio69 */ + TOP_MUX(0x4, "VGA"), /* sda */ + TOP_MUX(0x5, "B_DVI0")), /* d4 */ + TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18, + TOP_MUX(0x0, "I2S1"), /* mclk */ + TOP_MUX(0x1, "TSI1"), /* clk */ + TOP_MUX(0x2, "LCD"), /* dat18 */ + TOP_MUX(0x3, "BGPIO")), /* gpio70 */ + TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0, + TOP_MUX(0x0, "I2S1"), /* din0 */ + TOP_MUX(0x1, "TSI1"), /* sync */ + TOP_MUX(0x2, "LCD"), /* dat19 */ + TOP_MUX(0x3, "BGPIO")), /* gpio71 */ + TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9, + TOP_MUX(0x0, "I2S1"), /* dout0 */ + TOP_MUX(0x1, "TSI1"), /* valid */ + TOP_MUX(0x2, "LCD"), /* dat20 */ + TOP_MUX(0x3, "BGPIO")), /* gpio72 */ + TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18, + TOP_MUX(0x0, "SPI3"), /* clk */ + TOP_MUX(0x1, "TSO1"), /* clk */ + TOP_MUX(0x2, "LCD"), /* dat21 */ + TOP_MUX(0x3, "BGPIO"), /* gpio73 */ + TOP_MUX(0x4, "UART5"), /* rxd */ + TOP_MUX(0x5, "PCM"), /* fs */ + TOP_MUX(0x6, "I2S0"), /* din1 */ + TOP_MUX(0x7, "B_DVI0")), /* d5 */ + TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0, + TOP_MUX(0x0, "SPI3"), /* cs */ + TOP_MUX(0x1, "TSO1"), /* dat0 */ + TOP_MUX(0x2, "LCD"), /* dat22 */ + TOP_MUX(0x3, "BGPIO"), /* gpio74 */ + TOP_MUX(0x4, "UART5"), /* txd */ + TOP_MUX(0x5, "PCM"), /* clk */ + TOP_MUX(0x6, "I2S0"), /* din2 */ + TOP_MUX(0x7, "B_DVI0")), /* d6 */ + TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9, + TOP_MUX(0x0, "SPI3"), /* txd */ + TOP_MUX(0x1, "TSO1"), /* dat1 */ + TOP_MUX(0x2, "LCD"), /* dat23 */ + TOP_MUX(0x3, "BGPIO"), /* gpio75 */ + TOP_MUX(0x4, "UART5"), /* cts */ + TOP_MUX(0x5, "PCM"), /* txd */ + TOP_MUX(0x6, "I2S0"), /* din3 */ + TOP_MUX(0x7, "B_DVI0")), /* d7 */ + TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0, + TOP_MUX(0x0, "NAND"), /* ldo_ms18_sel */ + TOP_MUX(0x1, "BGPIO")), /* gpio99 */ + + /* top_pmm_reg_6 */ + TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18, + TOP_MUX(0x0, "SPI3"), /* rxd */ + TOP_MUX(0x1, "TSO1"), /* dat2 */ + TOP_MUX(0x2, "LCD"), /* stvu_vsync */ + TOP_MUX(0x3, "BGPIO"), /* gpio76 */ + TOP_MUX(0x4, "UART5"), /* rts */ + TOP_MUX(0x5, "PCM"), /* rxd */ + TOP_MUX(0x6, "I2S0"), /* dout1 */ + TOP_MUX(0x7, "B_DVI1")), /* clk */ + TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0, + TOP_MUX(0x0, "I2S0"), /* mclk */ + TOP_MUX(0x1, "TSO1"), /* dat3 */ + TOP_MUX(0x2, "LCD"), /* stvd */ + TOP_MUX(0x3, "BGPIO"), /* gpio77 */ + TOP_MUX(0x4, "USIM0"), /* cd */ + TOP_MUX(0x5, "B_DVI1")), /* vs */ + TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9, + TOP_MUX(0x0, "I2S0"), /* bclk */ + TOP_MUX(0x1, "TSO1"), /* dat4 */ + TOP_MUX(0x2, "LCD"), /* sthl_hsync */ + TOP_MUX(0x3, "BGPIO"), /* gpio78 */ + TOP_MUX(0x4, "USIM0"), /* clk */ + TOP_MUX(0x5, "B_DVI1")), /* hs */ + TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18, + TOP_MUX(0x0, "I2S0"), /* ws */ + TOP_MUX(0x1, "TSO1"), /* dat5 */ + TOP_MUX(0x2, "LCD"), /* sthr */ + TOP_MUX(0x3, "BGPIO"), /* gpio79 */ + TOP_MUX(0x4, "USIM0"), /* rst */ + TOP_MUX(0x5, "B_DVI1")), /* d0 */ + TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0, + TOP_MUX(0x0, "I2S0"), /* din0 */ + TOP_MUX(0x1, "TSO1"), /* dat6 */ + TOP_MUX(0x2, "LCD"), /* oev_dataen */ + TOP_MUX(0x3, "BGPIO"), /* gpio80 */ + TOP_MUX(0x4, "USIM0"), /* dat */ + TOP_MUX(0x5, "B_DVI1")), /* d1 */ + TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9, + TOP_MUX(0x0, "I2S0"), /* dout0 */ + TOP_MUX(0x1, "TSO1"), /* dat7 */ + TOP_MUX(0x2, "LCD"), /* ckv */ + TOP_MUX(0x3, "BGPIO")), /* gpio81 */ + TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18, + TOP_MUX(0x0, "I2C5"), /* scl */ + TOP_MUX(0x1, "TSO1"), /* sync */ + TOP_MUX(0x2, "LCD"), /* ld */ + TOP_MUX(0x3, "BGPIO"), /* gpio82 */ + TOP_MUX(0x4, "PWM"), /* out2 */ + TOP_MUX(0x5, "I2S0"), /* dout2 */ + TOP_MUX(0x6, "B_DVI1")), /* d2 */ + TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0, + TOP_MUX(0x0, "I2C5"), /* sda */ + TOP_MUX(0x1, "TSO1"), /* vld */ + TOP_MUX(0x2, "LCD"), /* pol */ + TOP_MUX(0x3, "BGPIO"), /* gpio83 */ + TOP_MUX(0x4, "PWM"), /* out3 */ + TOP_MUX(0x5, "I2S0"), /* dout3 */ + TOP_MUX(0x6, "B_DVI1")), /* d3 */ + TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9, + TOP_MUX(0x0, "SPI2"), /* clk */ + TOP_MUX(0x1, "TSO0"), /* clk */ + TOP_MUX(0x2, "LCD"), /* degsl */ + TOP_MUX(0x3, "BGPIO"), /* gpio84 */ + TOP_MUX(0x4, "I2C4"), /* scl */ + TOP_MUX(0x5, "B_DVI1")), /* d4 */ + TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18, + TOP_MUX(0x0, "SPI2"), /* cs */ + TOP_MUX(0x1, "TSO0"), /* data */ + TOP_MUX(0x2, "LCD"), /* rev */ + TOP_MUX(0x3, "BGPIO"), /* gpio85 */ + TOP_MUX(0x4, "I2C4"), /* sda */ + TOP_MUX(0x5, "B_DVI1")), /* d5 */ + TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0, + TOP_MUX(0x0, "SPI2"), /* txd */ + TOP_MUX(0x1, "TSO0"), /* sync */ + TOP_MUX(0x2, "LCD"), /* u_d */ + TOP_MUX(0x3, "BGPIO"), /* gpio86 */ + TOP_MUX(0x4, "I2C4"), /* scl */ + TOP_MUX(0x5, "B_DVI1")), /* d6 */ + + /* top_pmm_reg_7 */ + TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9, + TOP_MUX(0x0, "SPI2"), /* rxd */ + TOP_MUX(0x1, "TSO0"), /* vld */ + TOP_MUX(0x2, "LCD"), /* r_l */ + TOP_MUX(0x3, "BGPIO"), /* gpio87 */ + TOP_MUX(0x4, "I2C3"), /* sda */ + TOP_MUX(0x5, "B_DVI1")), /* d7 */ + TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9, + TOP_MUX(0x0, "NAND"), /* wp */ + TOP_MUX(0x1, "PWM"), /* out2 */ + TOP_MUX(0x2, "SPI2"), /* clk */ + TOP_MUX(0x3, "BGPIO"), /* gpio88 */ + TOP_MUX(0x4, "TSI0"), /* dat0 */ + TOP_MUX(0x5, "I2S1")), /* din1 */ + TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0, + TOP_MUX(0x0, "NAND"), /* boot_pagesize0 */ + TOP_MUX(0x1, "PWM"), /* out3 */ + TOP_MUX(0x2, "SPI2"), /* cs */ + TOP_MUX(0x3, "BGPIO"), /* gpio89 */ + TOP_MUX(0x4, "TSI0"), /* clk */ + TOP_MUX(0x5, "I2S1")), /* din2 */ + TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9, + TOP_MUX(0x0, "NAND"), /* boot_pagesize1 */ + TOP_MUX(0x1, "I2C4"), /* scl */ + TOP_MUX(0x2, "SPI2"), /* txd */ + TOP_MUX(0x3, "BGPIO"), /* gpio90 */ + TOP_MUX(0x4, "TSI0"), /* sync */ + TOP_MUX(0x5, "I2S1")), /* din3 */ + TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18, + TOP_MUX(0x0, "NAND"), /* boot_addr_cycles */ + TOP_MUX(0x1, "I2C4"), /* sda */ + TOP_MUX(0x2, "SPI2"), /* rxd */ + TOP_MUX(0x3, "BGPIO"), /* gpio91 */ + TOP_MUX(0x4, "TSI0"), /* valid */ + TOP_MUX(0x5, "I2S1")), /* dout1 */ + TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0, + TOP_MUX(0x0, "NAND"), /* rdy_busy0 */ + TOP_MUX(0x1, "I2C2"), /* scl */ + TOP_MUX(0x2, "USIM0"), /* cd */ + TOP_MUX(0x3, "BGPIO"), /* gpio92 */ + TOP_MUX(0x4, "TSI1")), /* data0 */ + TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9, + TOP_MUX(0x0, "NAND"), /* rdy_busy1 */ + TOP_MUX(0x1, "I2C2"), /* sda */ + TOP_MUX(0x2, "USIM0"), /* clk */ + TOP_MUX(0x3, "BGPIO"), /* gpio93 */ + TOP_MUX(0x4, "TSI1")), /* clk */ + TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18, + TOP_MUX(0x0, "NAND"), /* rdy_busy2 */ + TOP_MUX(0x1, "UART5"), /* rxd */ + TOP_MUX(0x2, "USIM0"), /* rst */ + TOP_MUX(0x3, "BGPIO"), /* gpio94 */ + TOP_MUX(0x4, "TSI1"), /* sync */ + TOP_MUX(0x4, "I2S1")), /* dout2 */ + TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18, + TOP_MUX(0x0, "NAND"), /* rdy_busy3 */ + TOP_MUX(0x1, "UART5"), /* txd */ + TOP_MUX(0x2, "USIM0"), /* dat */ + TOP_MUX(0x3, "BGPIO"), /* gpio95 */ + TOP_MUX(0x4, "TSI1"), /* valid */ + TOP_MUX(0x4, "I2S1")), /* dout3 */ + + /* top_pmm_reg_8 */ + TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0, + TOP_MUX(0x0, "GMII"), /* 125m_in */ + TOP_MUX(0x1, "USB2"), /* 0_drvvbus */ + TOP_MUX(0x2, "ISP"), /* ref_clk */ + TOP_MUX(0x3, "BGPIO")), /* gpio96 */ + TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9, + TOP_MUX(0x0, "GMII"), /* 50m_out */ + TOP_MUX(0x1, "USB2"), /* 1_drvvbus */ + TOP_MUX(0x2, "BGPIO"), /* gpio97 */ + TOP_MUX(0x3, "USB2")), /* 0_drvvbus */ + TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9, + TOP_MUX(0x0, "SPINOR")), /* sdio1_clk_i */ + TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18, + TOP_MUX(0x0, "SPINOR")), /* ssclk_i */ +}; + +static struct zx_pinctrl_soc_info zx296718_pinctrl_info = { + .pins = zx296718_pins, + .npins = ARRAY_SIZE(zx296718_pins), +}; + +static int zx296718_pinctrl_probe(struct platform_device *pdev) +{ + return zx_pinctrl_init(pdev, &zx296718_pinctrl_info); +} + +static const struct of_device_id zx296718_pinctrl_match[] = { + { .compatible = "zte,zx296718-pmm", }, + {} +}; +MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match); + +static struct platform_driver zx296718_pinctrl_driver = { + .probe = zx296718_pinctrl_probe, + .driver = { + .name = "zx296718-pinctrl", + .of_match_table = zx296718_pinctrl_match, + }, +}; +builtin_platform_driver(zx296718_pinctrl_driver); + +MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver"); +MODULE_LICENSE("GPL"); |