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* Merge tag 'soc-drivers-6.2' of ↵Linus Torvalds2022-12-12118-1876/+6540
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Arnd Bergmann: "There are few major updates in the SoC specific drivers, mainly the usual reworks and support for variants of the existing SoC. While this remains Arm centric for the most part, the branch now also contains updates to risc-v and loongarch specific code in drivers/soc/. Notable changes include: - Support for the newly added Qualcomm Snapdragon variants (MSM8956, MSM8976, SM6115, SM4250, SM8150, SA8155 and SM8550) in the soc ID, rpmh, rpm, spm and powerdomain drivers. - Documentation for the somewhat controversial qcom,board-id properties that are required for booting a number of machines - A new SoC identification driver for the loongson-2 (loongarch) platform - memory controller updates for stm32, tegra, and renesas. - a new DT binding to better describe LPDDR2/3/4/5 chips in the memory controller subsystem - Updates for Tegra specific drivers across multiple subsystems, improving support for newer SoCs and better identification - Minor fixes for Broadcom, Freescale, Apple, Renesas, Sifive, TI, Mediatek and Marvell SoC drivers" * tag 'soc-drivers-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (137 commits) soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for SM6115 / SM4250 and variants soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for SM8150 and SA8155 dt-bindings: soc: qcom: apr: document generic qcom,apr compatible soc: qcom: Select REMAP_MMIO for ICC_BWMON driver soc: qcom: Select REMAP_MMIO for LLCC driver soc: qcom: rpmpd: Add SM4250 support dt-bindings: power: rpmpd: Add SM4250 support dt-bindings: soc: qcom: aoss: Add compatible for SM8550 soc: qcom: llcc: Add configuration data for SM8550 dt-bindings: arm: msm: Add LLCC compatible for SM8550 soc: qcom: llcc: Add v4.1 HW version support soc: qcom: socinfo: Add SM8550 ID soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done response soc: qcom: rpmh-rsc: Add support for RSC v3 register offsets soc: qcom: rpmhpd: Add SM8550 power domains dt-bindings: power: rpmpd: Add SM8550 to rpmpd binding soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976 ...
| * Merge tag 'qcom-drivers-for-6.2-2' of ↵Arnd Bergmann2022-12-0716-101/+383
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers More Qualcomm driver updates for 6.2 Socinfo is extended with knowledge about MSM8956, MSM8976, SM6115, SM4250, SM8150, SA8155 and SM8550. Support for RSC v3, as found in SM8550 is added to the RPMH RSC driver. Support for SM8550 and SM4250 ARC regulators are added to the RPM(h) power-domain drivers. SM8550 support is added to the LLCC driver. The AOSS QMP binding is declared compatible for SM8550. BWMON and LLCC now selects REGMAP_MMIO to ensure dependencies are built properly. * tag 'qcom-drivers-for-6.2-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for SM6115 / SM4250 and variants soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for SM8150 and SA8155 dt-bindings: soc: qcom: apr: document generic qcom,apr compatible soc: qcom: Select REMAP_MMIO for ICC_BWMON driver soc: qcom: Select REMAP_MMIO for LLCC driver soc: qcom: rpmpd: Add SM4250 support dt-bindings: power: rpmpd: Add SM4250 support dt-bindings: soc: qcom: aoss: Add compatible for SM8550 soc: qcom: llcc: Add configuration data for SM8550 dt-bindings: arm: msm: Add LLCC compatible for SM8550 soc: qcom: llcc: Add v4.1 HW version support soc: qcom: socinfo: Add SM8550 ID soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done response soc: qcom: rpmh-rsc: Add support for RSC v3 register offsets soc: qcom: rpmhpd: Add SM8550 power domains dt-bindings: power: rpmpd: Add SM8550 to rpmpd binding soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976 Link: https://lore.kernel.org/r/20221207154134.3233779-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * soc: qcom: socinfo: Add SM6115 / SM4250 SoC IDs to the soc_id tableBhupesh Sharma2022-12-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SoC ID table entries for the SM6115 / SM4250 and variants. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-5-bhupesh.sharma@linaro.org
| | * dt-bindings: arm: qcom,ids: Add SoC IDs for SM6115 / SM4250 and variantsBhupesh Sharma2022-12-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SoC IDs for Qualcomm SM6115 / SM4250 and variants. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-4-bhupesh.sharma@linaro.org
| | * soc: qcom: socinfo: Add SM8150 and SA8155 SoC IDs to the soc_id tableBhupesh Sharma2022-12-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SoC ID table entries for the SM8150 and SA8155 SoCs. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-3-bhupesh.sharma@linaro.org
| | * dt-bindings: arm: qcom,ids: Add SoC IDs for SM8150 and SA8155Bhupesh Sharma2022-12-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SoC IDs for Qualcomm SM8150 and SA8155 SoCs. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201141619.2462705-2-bhupesh.sharma@linaro.org
| | * dt-bindings: soc: qcom: apr: document generic qcom,apr compatibleKrzysztof Kozlowski2022-12-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document the qcom,apr compatible, used by Qualcomm Asynchronous Packet Router driver. There are no upstream DTSes using this compatible - instead we have ones with APRv2 (qcom,apr-v2). The driver does not make distinction between both compatibles, which raises the question whether the compatible is really needed. Document it (as compatible with v2) for completeness. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221201133637.46146-1-krzysztof.kozlowski@linaro.org
| | * soc: qcom: Select REMAP_MMIO for ICC_BWMON driverManivannan Sadhasivam2022-12-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICC_BWMON driver uses REGMAP_MMIO for accessing the hardware registers. So select the dependency in Kconfig. Without this, there will be errors while building the driver with COMPILE_TEST only: ERROR: modpost: "__devm_regmap_init_mmio_clk" [drivers/soc/qcom/icc-bwmon.ko] undefined! make[1]: *** [scripts/Makefile.modpost:126: Module.symvers] Error 1 make: *** [Makefile:1944: modpost] Error 2 Cc: <stable@vger.kernel.org> # 6.0 Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Fixes: b9c2ae6cac40 ("soc: qcom: icc-bwmon: Add bandwidth monitoring driver") Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221129072022.41962-1-manivannan.sadhasivam@linaro.org
| | * soc: qcom: Select REMAP_MMIO for LLCC driverManivannan Sadhasivam2022-12-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LLCC driver uses REGMAP_MMIO for accessing the hardware registers. So select the dependency in Kconfig. Without this, there will be errors while building the driver with COMPILE_TEST only: ERROR: modpost: "__devm_regmap_init_mmio_clk" [drivers/soc/qcom/llcc-qcom.ko] undefined! make[1]: *** [scripts/Makefile.modpost:126: Module.symvers] Error 1 make: *** [Makefile:1944: modpost] Error 2 Cc: <stable@vger.kernel.org> # 4.19 Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver") Reported-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221129071201.30024-2-manivannan.sadhasivam@linaro.org
| | * soc: qcom: rpmpd: Add SM4250 supportBhupesh Sharma2022-12-051-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SM4250 has the same RPM power domains as SM6115. Add SM4250 support by reusing SM6115 power domains. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221127112204.1486337-3-bhupesh.sharma@linaro.org
| | * dt-bindings: power: rpmpd: Add SM4250 supportBhupesh Sharma2022-12-052-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add compatible and constants for the power domains exposed by the SM4250 RPM. Cc: Bjorn Andersson <andersson@kernel.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Konrad Dybcio <konrad.dybcio@somainline.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221127112204.1486337-2-bhupesh.sharma@linaro.org
| | * dt-bindings: soc: qcom: aoss: Add compatible for SM8550Abel Vesa2022-12-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Document the compatible for SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113128.2655441-1-abel.vesa@linaro.org
| | * soc: qcom: llcc: Add configuration data for SM8550Abel Vesa2022-12-052-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | Add LLCC configuration data for SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113005.2653284-4-abel.vesa@linaro.org
| | * dt-bindings: arm: msm: Add LLCC compatible for SM8550Abel Vesa2022-12-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add LLCC compatible for SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113005.2653284-3-abel.vesa@linaro.org
| | * soc: qcom: llcc: Add v4.1 HW version supportAbel Vesa2022-12-051-7/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The LLCC found in SM8550 supports more slice configuration knobs and HW block version has been bumped up to 4.1. Add support for the new version and make sure the new config values are programed on probe. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116113005.2653284-2-abel.vesa@linaro.org
| | * soc: qcom: socinfo: Add SM8550 IDAbel Vesa2022-12-052-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ID for the Qualcomm SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112438.2643607-1-abel.vesa@linaro.org
| | * soc: qcom: rpmh-rsc: Avoid unnecessary checks on irq-done responseAbel Vesa2022-12-054-37/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RSC interrupt is issued only after the request is complete. For fire-n-forget requests, the irq-done interrupt is sent after issuing the RPMH request and for response-required request, the interrupt is triggered only after all the requests are complete. These unnecessary checks in the interrupt handler issues AHB reads from a critical path. Lets remove them and clean up error handling in rpmh_request data structures. Co-developed-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112246.2640648-2-abel.vesa@linaro.org
| | * soc: qcom: rpmh-rsc: Add support for RSC v3 register offsetsAbel Vesa2022-12-052-58/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SM8550 RSC has a new set of register offsets due to its version bump. So read the version from HW and use the proper register offsets based on that. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116112246.2640648-1-abel.vesa@linaro.org
| | * soc: qcom: rpmhpd: Add SM8550 power domainsAbel Vesa2022-12-051-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the power domains exposed by RPMH in the Qualcomm SM8550 platform. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116111745.2633074-3-abel.vesa@linaro.org
| | * dt-bindings: power: rpmpd: Add SM8550 to rpmpd bindingAbel Vesa2022-12-052-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SM8550 platform. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221116111745.2633074-2-abel.vesa@linaro.org
| | * soc: qcom: socinfo: Add MSM8956/76 SoC IDs to the soc_id tableAngeloGioacchino Del Regno2022-12-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SoC ID table entries for MSM8956 and MSM8976 chips. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111120156.48040-8-angelogioacchino.delregno@collabora.com
| | * dt-bindings: arm: qcom,ids: Add SoC IDs for MSM8956 and MSM8976AngeloGioacchino Del Regno2022-12-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Document the identifier of MSM8956/76. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111120156.48040-7-angelogioacchino.delregno@collabora.com
| * | soc: fsl: qe: request pins non-exclusivelyDmitry Torokhov2022-12-053-30/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()") changed qe_pin_request() to request and hold GPIO corresponding to a given pin. Unfortunately this does not work, as fhci-hcd requests these GPIOs first, befor calling qe_pin_request() (see drivers/usb/host/fhci-hcd.c::of_fhci_probe()). To fix it change qe_pin_request() to request GPIOs non-exclusively, and free them once the code determines GPIO controller and offset for each GPIO/pin. Also reaching deep into gpiolib implementation is not the best idea. We should either export gpio_chip_hwgpio() or keep converting to the global gpio numbers space until we fix the driver to implement proper pin control. Fixes: 84582f9ed090 ("soc: fsl: qe: Avoid using gpio_to_desc()") Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/Y400YXnWBdz1e/L5@google.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: mmp: fix timer_read delayDoug Brown2022-12-041-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | timer_read() was using an empty 100-iteration loop to wait for the TMR_CVWR register to capture the latest timer counter value. The delay wasn't long enough. This resulted in CPU idle time being extremely underreported on PXA168 with CONFIG_NO_HZ_IDLE=y. Switch to the approach used in the vendor kernel, which implements the capture delay by reading TMR_CVWR a few times instead. Fixes: 49cbe78637eb ("[ARM] pxa: add base support for Marvell's PXA168 processor line") Signed-off-by: Doug Brown <doug@schmorgal.com> Link: https://lore.kernel.org/r/20221204005117.53452-3-doug@schmorgal.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | pxa: Remove dev_err() after platform_get_irq()zhang songyi2022-12-041-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to call the dev_err() function directly to print a custom message when handling an error from either the platform_get_irq() or platform_get_irq_byname() functions as both are going to display an appropriate error message in case of a failure. Signed-off-by: zhang songyi <zhang.songyi@zte.com.cn> Reviewed-by: Lubomir Rintel <lkundrak@v3.sk> Link: https://lore.kernel.org/r/202212021042043546303@zte.com.cn Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | Merge tag 'arm-soc/for-6.2/drivers' of https://github.com/Broadcom/stblinux ↵Arnd Bergmann2022-11-304-6/+30
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into soc/drivers This pull request contains Broadcom SoCs driver changes for 6.2, please pull the following: - Yuan uses dev_err_probe() in the Raspberry Pi firmware provider to simplify the error handling code - Rafal adds support for initialiazing the BCM47xx NVMEM/NVRAM firmware provider out of memory-mapped flash devices. * tag 'arm-soc/for-6.2/drivers' of https://github.com/Broadcom/stblinux: firmware/nvram: bcm47xx: support init from IO memory firmware: raspberrypi: Use dev_err_probe() to simplify code Link: https://lore.kernel.org/r/20221129191755.542584-3-f.fainelli@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | firmware/nvram: bcm47xx: support init from IO memoryRafał Miłecki2022-11-093-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide NVMEM content to the NVRAM driver from a simple memory resource. This is necessary to use NVRAM in a memory- mapped flash device. Patch taken from OpenWrts development tree. This patch makes it possible to use memory-mapped NVRAM on the D-Link DWL-8610AP and the D-Link DIR-890L. Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@vger.kernel.org Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Rafał Miłecki <rafal@milecki.pl> [Added an export for modules potentially using the init symbol] Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20221103082529.359084-1-linus.walleij@linaro.org Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * | firmware: raspberrypi: Use dev_err_probe() to simplify codeYuan Can2022-10-171-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the probe path, dev_err() can be replaced with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. It also sets the defer probe reason which can be checked later through debugfs. Signed-off-by: Yuan Can <yuancan@huawei.com> Link: https://lore.kernel.org/r/20220924025041.29389-1-yuancan@huawei.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | | Merge tag 'asahi-soc-rtkit-sart-6.2' of https://github.com/AsahiLinux/linux ↵Arnd Bergmann2022-11-302-4/+10
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into soc/drivers Apple SoC RTKit/SART updates for 6.2. Just two minor correctness nits reported by the kernel test robot. * tag 'asahi-soc-rtkit-sart-6.2' of https://github.com/AsahiLinux/linux: soc: apple: rtkit: Stop casting function pointer signatures soc: apple: sart: Stop casting function pointer signatures Link: https://lore.kernel.org/r/57f84134-8645-35f6-2427-ee683800c413@marcan.st Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | | soc: apple: rtkit: Stop casting function pointer signaturesSven Peter2022-11-281-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes: 9bd1d9a0d8bb ("soc: apple: Add RTKit IPC library") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
| | * | | soc: apple: sart: Stop casting function pointer signaturesSven Peter2022-11-281-1/+6
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | Fixes: b170143ae111 ("soc: apple: Add SART driver") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
| * | | tegra: mark BPMP driver as little-endian onlyArnd Bergmann2022-11-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BPMP firmware driver never worked on big-endian kernels, and cannot easily be made portable. Add a dependency to make this clear in case anyone ever wants to try a big-endian kernel on this hardware. Link: https://lore.kernel.org/linux-arm-kernel/Y34FCQ3xTmcjqKRT@orome/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | Merge tag 'ti-driver-soc-for-v6.2-v2' of ↵Arnd Bergmann2022-11-236-18/+41
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/drivers TI SoC driver updates for v6.2 v2 * Minor bugfixes for knav_qmss_queue, smartreflex drivers * API optimizations including using devm, bitmap apis to ti-sci, soc-info drivers * k3-ringacc can now be built as modules for certain distros that mandate such usage. * k3-socinfo can now detect AM62A SoCs. * tag 'ti-driver-soc-for-v6.2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: soc: ti: k3-socinfo: Add AM62Ax JTAG ID soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probe soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probe firmware: ti_sci: Use devm_bitmap_zalloc when applicable soc: ti: k3-ringacc: Allow the driver to be built as module firmware: ti_sci: Fix polled mode during system suspend firmware: ti_sci: Use the non-atomic bitmap API when applicable firmware: ti_sci: Use the bitmap API to allocate bitmaps drivers: soc: ti: knav_qmss_queue: Mark knav_acc_firmwares as static Link: https://lore.kernel.org/r/20221122223856.fwackjg7fbd5jcz7@wannabe Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | | soc: ti: k3-socinfo: Add AM62Ax JTAG IDVignesh Raghavendra2022-11-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add JTAG ID entry to help identify AM62Ax SoC in kernel. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221119152447.241166-1-vigneshr@ti.com
| | * | | soc: ti: smartreflex: Fix PM disable depth imbalance in omap_sr_probeZhang Qilong2022-11-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes: 984aa6dbf4ca ("OMAP3: PM: Adding smartreflex driver support.") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221108080322.52268-3-zhangqilong3@huawei.com
| | * | | soc: ti: knav_qmss_queue: Fix PM disable depth imbalance in knav_queue_probeZhang Qilong2022-11-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. Fixes: 41f93af900a2 ("soc: ti: add Keystone Navigator QMSS driver") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221108080322.52268-2-zhangqilong3@huawei.com
| | * | | firmware: ti_sci: Use devm_bitmap_zalloc when applicableChristophe JAILLET2022-11-031-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'xfer_alloc_table' is a bitmap. So use 'devm_bitmap_zalloc()' to simplify code and improve the semantic of the code. While at it, remove a redundant 'bitmap_zero()' call. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/43ab1a7dd073d0d037d5d4bbbd5f8335de605826.1667457664.git.christophe.jaillet@wanadoo.fr
| | * | | soc: ti: k3-ringacc: Allow the driver to be built as modulePeter Ujfalusi2022-11-032-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ring accelerator driver can be built as module since all depending functions are exported. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Nicolas Frayer <nfrayer@baylibre.com> Reviewed-by: Nicolas Frayer <nfrayer@baylibre.com> Link: https://lore.kernel.org/r/20221029075356.7296-1-peter.ujfalusi@gmail.com
| | * | | firmware: ti_sci: Fix polled mode during system suspendGeorgi Vlaev2022-10-281-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b9e8a7d950ff ("firmware: ti_sci: Switch transport to polled mode during system suspend") uses read_poll_timeout_atomic() macro in ti_sci_do_xfer() to wait for completion when the system is suspending. The break condition of the macro is set to "true" which will cause it break immediately when evaluated, likely before the TISCI xfer is completed, and always return 0. We want to poll here until "done_state == true". 1) Change the break condition of read_poll_timeout_atomic() to the bool variable "done_state". 2) The read_poll_timeout_atomic() returns 0 if the break condition is met or -ETIMEDOUT if not. Since our break condition has changed to "done_state", we also don't have to check for "!done_state" when evaluating the return value. Fixes: b9e8a7d950ff ("firmware: ti_sci: Switch transport to polled mode during system suspend") Signed-off-by: Georgi Vlaev <g-vlaev@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221021185704.181316-1-g-vlaev@ti.com
| | * | | firmware: ti_sci: Use the non-atomic bitmap API when applicableChristophe JAILLET2022-10-281-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Usages of the 'res_map' bitmap is protected with a spinlock, so non-atomic functions can be used to set/clear bits. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/fb7edc555b6fa7c74707f13e422196693a834bc8.1657308216.git.christophe.jaillet@wanadoo.fr
| | * | | firmware: ti_sci: Use the bitmap API to allocate bitmapsChristophe JAILLET2022-10-281-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use devm_bitmap_zalloc() instead of hand-writing them. It is less verbose and it improves the semantic. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/3ee11e9e83f7c1552d237f5c28f554319fcbbf1f.1657308216.git.christophe.jaillet@wanadoo.fr
| | * | | drivers: soc: ti: knav_qmss_queue: Mark knav_acc_firmwares as staticChen Jiahao2022-10-281-1/+1
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a sparse warning shown below: drivers/soc/ti/knav_qmss_queue.c:70:12: warning: symbol 'knav_acc_firmwares' was not declared. Should it be static? Since 'knav_acc_firmwares' is only called within knav_qmss_queue.c, mark it as static to fix the warning. Fixes: 96ee19becc3b ("soc: ti: add firmware file name as part of the driver") Signed-off-by: Chen Jiahao <chenjiahao16@huawei.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20221019153212.72350-1-chenjiahao16@huawei.com
| * | | Merge tag 'qcom-drivers-for-6.2' of ↵Arnd Bergmann2022-11-2327-170/+817
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers Qualcomm driver updates for 6.2 The qcom,msm-id and qcom,board-id DeviceTree properties are documented, to allow them to be used in configurations or devices requiring these and the socinfo driver is updated to reuse the introduced identifiers. The rpmh-rsc driver is extended to register for PM runtime notifications from the CPU clusters, in order to submit sleep and wake votes the last core in a cluster is being powered down. A mechanism for keeping rpmhpd resources voted until sync_state is introduced, this ensures that power-domains required during boot are kept enabled. The rpmhpd power-domains for SDM670 are also added. Support for the new QDU1000/QRU1000 platform is introduced in the rpmhpd and socinfo drivers. The APR driver gains missing error handling. QMI message descriptors in the PDR driver are made const. Support for the RPM found in SM6375 is added. The SPM driver gains support for MSM8939 and MSM8976 platforms. The stats and command-db drvers are marked as not having PM support. * tag 'qcom-drivers-for-6.2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (36 commits) dt-bindings: firmware: scm: add sdm670 compatible soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup soc: qcom: rpmh-rsc: Save base address of drv PM: domains: Store the next hrtimer wakeup in genpd soc: qcom: rpmh-rsc: Attach RSC to cluster PM domain dt-bindings: soc: qcom: Update devicetree binding document for rpmh-rsc dt-bindings: soc: qcom: qcom,smd-rpm: Use qcom,smd-channels on MSM8976 soc: qcom: apr: Add check for idr_alloc and of_property_read_string_index soc: qcom: socinfo: Add QDU1000/QRU1000 SoC IDs to the soc_id table dt-bindings: arm: qcom,ids: Add SoC IDs for QDU1000/QRU1000 soc: qcom: rpmhpd: Add QDU1000/QRU1000 power domains dt-bindings: power: rpmpd: Add QDU1000/QRU1000 to rpmpd binding dt-bindings: qcom: smp2p: Add WPSS node names to pattern property soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2 soc: qcom: llcc: make irq truly optional soc: qcom: spm: Add MSM8939 SPM register data dt-bindings: soc: qcom: spm: Add MSM8939 CPU compatible dt-bindings: soc: qcom: aoss: Add sc8280xp compatible dt-bindings: firmware: document Qualcomm SM6375 SCM ... Link: https://lore.kernel.org/r/20221122202748.1854487-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| | * | dt-bindings: firmware: scm: add sdm670 compatibleRichard Acayan2022-11-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Snapdragon 670 uses SCM as for PSCI power management. Document the appropriate compatible string for it. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221111001818.124901-4-mailingradian@gmail.com
| | * | soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeupMaulik Shah2022-11-093-1/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The next wakeup timer value needs to be set in always on domain timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state. To wakeup the SoC in such scenarios the earliest wakeup time is set in CONTROL_TCS and the firmware takes care of setting up its own timer in always on domain with next wakeup time. The timer wakes up the RSC and sets resources back to wake state. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson@linaro.org
| | * | soc: qcom: rpmh-rsc: Save base address of drvMaulik Shah2022-11-092-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add changes to save drv's base address for rsc. This is used to read drv's configuration such as solver mode is supported or to write into CONTROL_TCS registers. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-6-ulf.hansson@linaro.org
| | * | PM: domains: Store the next hrtimer wakeup in genpdMaulik Shah2022-11-093-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arch timer cannot wake up the Qualcomm Technologies, Inc. (QTI) SoCs from the deeper CPUidle states. To be able to wakeup from these deeper states, another always-on timer needs to be programmed through the so called CONTROL_TCS. As the RSC is part of CPU subsystem and the corresponding APSS RSC device is attached to the cluster PM domain (through genpd), it holds the responsibility to program the always-on timer, before entering any of these deeper CPUidle states. However, programming the timer requires information about the next hrtimer wakeup for the cluster PM domain, which is currently only known by genpd. Therefore, let's share this data through a new genpd helper function, dev_pm_genpd_get_next_hrtimer(). Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Cc: "Rafael J. Wysocki" <rafael@kernel.org> [Ulf: Reworked the code and updated the commit message] Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-5-ulf.hansson@linaro.org
| | * | soc: qcom: rpmh-rsc: Attach RSC to cluster PM domainLina Iyer2022-11-092-5/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RSC is part the CPU subsystem and powers off the CPU domains when all the CPUs and no RPMH transactions are pending from any of the drivers. The RSC needs to flush the 'sleep' and 'wake' votes that are critical for saving power when all the CPUs are in idle. Let's make RSC part of the CPU PM domains, by attaching it to the cluster power domain. Registering for PM domain notifications, RSC driver can be notified that the last CPU is powering down. When the last CPU is powering down the domain, let's flush the 'sleep' and 'wake' votes that are stored in the data buffers into the hardware and also write next wakeup in CONTROL_TCS. Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-3-ulf.hansson@linaro.org
| | * | dt-bindings: soc: qcom: Update devicetree binding document for rpmh-rscMaulik Shah2022-11-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The change documents power-domains property for RSC device. This optional property points to corresponding PM domain node. Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-2-ulf.hansson@linaro.org
| | * | dt-bindings: soc: qcom: qcom,smd-rpm: Use qcom,smd-channels on MSM8976AngeloGioacchino Del Regno2022-11-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like MSM8916 and some others, MSM8976 uses qcom,smd-channels and not qcom,glink-channels. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221104172122.252761-5-angelogioacchino.delregno@collabora.com
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