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| | * irqchip: intc-irqpin: Add support for shared interrupt linesBastian Hecht2013-03-281-7/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some hardware we don't have a 1-1 mapping from the external interrupts coming from INTC to the GIC SPI pins. We can however share lines to demux incoming IRQs on these SoCs. This patch enables the intc_irqpin driver to detect requests for shared interrupt lines and demuxes them properly by querying the INTC INTREQx0A registers. If you need multiple shared intc_irqpin device instances, be sure to mask out all interrupts on the INTC that share the one line before you start to register them. Else you run into IRQ floods that would be caused by interrupts for which no handler has been set up yet when the first intc_irqpin device is registered. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * irqchip: irqc: Add DT supportMagnus Damm2013-03-181-0/+9
| | | | | | | | | | | | | | | | | | | | | Add DT support to the IRQC External IRQ Pin driver. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * irqchip: intc-irqpin: Initial DT supportMagnus Damm2013-03-181-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial DT support to the INTC External IRQ Pin driver. At this point only hardware with 4-bit wide sense registers is supported via DT. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * ARM: shmobile: Make r8a7779 INTC irqpin platform data staticMagnus Damm2013-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The platform data for the INTC irq pin driver seems to be global symbols, make it static to allow multi-soc build. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * ARM: shmobile: Make sh73a0 INTC irqpin platform data staticMagnus Damm2013-03-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The platform data for the INTC irq pin driver seems to be global symbols, make it static to allow multi-soc build. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * irqchip: Renesas IRQC driverMagnus Damm2013-03-184-0/+330
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for external IRQ pins connected to the IRQC hardware block on recent SoCs from Renesas. The IRQC hardware block is used together with more recent ARM based SoCs using the GIC. As usual the GIC requires external IRQ trigger setup somewhere else which in this particular case happens to be IRQC. This driver implements the glue code needed to configure IRQ trigger and also handle mask/unmask and demux of external IRQ pins hooked up from the IRQC to the GIC. Tested on r8a73a4 but is designed to work with a wide range of SoCs. The driver requires one GIC SPI per external IRQ pin to operate. Each driver instance will handle up to 32 external IRQ pins. The SoCs using this driver are currently mainly used together with regular platform devices so this driver allows configuration via platform data to support things like static interrupt base address. DT support will be added incrementally in the not so distant future. Signed-off-by: Magnus Damm <damm@opensource.se> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * irqchip: intc-irqpin: GPL header for platform dataMagnus Damm2013-03-181-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add GPL header to platform data include file. Signed-off-by: Magnus Damm <damm@opensource.se> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * irqchip: intc-irqpin: Make use of devm functionsMagnus Damm2013-03-181-28/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use devm_kzalloc(), devm_ioremap_nocache() and devm_request_irq() to simplify error handling. Signed-off-by: Magnus Damm <damm@opensource.se> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * irqchip: intc-irqpin: Add force commentsMagnus Damm2013-03-181-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add comments to describe the special case for "force" versions of enable and disable functions. Signed-off-by: Magnus Damm <damm@opensource.se> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * irqchip: intc-irqpin: Cache mapped IRQMagnus Damm2013-03-181-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cache IRQ in domain_irq variable instead of making use of irq_find_mapping(). While at it rename the irq variable to requested_irq. Signed-off-by: Magnus Damm <damm@opensource.se> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * irqchip: intc-irqpin: Whitespace fixesMagnus Damm2013-03-181-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove whitespace damage and add newline between variables and code. Signed-off-by: Magnus Damm <damm@opensource.se> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * ARM: shmobile: INTC External IRQ pin driver on r8a7779Magnus Damm2013-03-183-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the r8a7779 IRQ code to make use of the INTC External IRQ pin driver for external interrupt pins IRQ0 -> IRQ3. The r8a7779 SoC can like older SH SoCs configure to use the IRQ0 -> IRQ3 signals as individual interrupts or a combined IRL mode. Without this patch the r8a7779 SoC code does not fully support external IRQ pins in individual IRQ mode. The r8a7779 PFC code does not yet have gpio_to_irq() support so no need to update such code. At this point the DT reference implementations are not covered. In the future such code shall tie in the INTC External IRQ pin driver via DT, so this kind of verbose code is not needed for the long term DT case. Signed-off-by: Magnus Damm <damm@opensource.se> Tested-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * ARM: shmobile: INTC External IRQ pin driver on sh73a0Magnus Damm2013-03-185-127/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the sh73a0 IRQ code to make use of the INTC External IRQ pin driver for external interrupt pins IRQ0 -> IRQ31. This removes quite a bit of special-case code in intc-sh73a0.c but the number of lines get replaced with platform device information in setup-sh73a0.c. The PFC code is also adjusted to make gpio_to_irq() return the correct interrupt number. At this point the DT reference implementations are not covered. In the future such code shall tie in the INTC External IRQ pin driver via DT, so this kind of verbose code is not needed for the long term DT case. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * ARM: shmobile: irq_pin() for static IRQ pin assignmentMagnus Damm2013-03-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add the macro irq_pin() to let board-specific code using platform devices tie in external IRQn pins in a common way. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| | * irqchip: Renesas INTC External IRQ pin driverMagnus Damm2013-03-184-0/+479
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for external IRQ pins connected to the INTC block on recent SoCs from Renesas. The INTC hardware block usually contains a rather wide range of features ranging from external IRQ pin handling to legacy interrupt controller support. On older SoCs the INTC is used as a general purpose interrupt controller both for external IRQ pins and on-chip devices. On more recent ARM based SoCs with Cortex-A9 the main interrupt controller is the GIC, but IRQ trigger setup still need to happen in the INTC hardware block. This driver implements the glue code needed to configure IRQ trigger and also handle mask/unmask and demux of external IRQ pins hooked up from the INTC to the GIC. Tested on sh73a0 and r8a7779. The hardware varies quite a bit with SoC model, for instance register width and bitfield widths vary wildly. The driver requires one GIC SPI per external IRQ pin to operate. Each driver instance will handle up to 8 external IRQ pins. The SoCs using this driver are currently mainly used together with regular platform devices so this driver allows configuration via platform data to support things like static interrupt base address. DT support will be added incrementally in the not so distant future. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * r8a7779: Add Display Unit clock supportPhil Edworthy2013-03-181-1/+3
| | | | | | | | | | | | | | | | Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> [Rename device from to rcarfb to rcar-du] Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> [Manual conflict resolution] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: R8A7779: use gic_iid() in SATA IRQ resourceSergei Shtylyov2013-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | Commit "ARM: shmobile: r8a7779: use gic_iid macro" switched R8A7779 platform devices to using gic_iid() macro instead of gic_spi() but commit "ARM: mach- shmobile: r8a7779: add SATA support" added another use of gic_spi(). Convert the SATA IRQ resource to using gic_iid(). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: mach-shmobile: r8a7779: add SATA supportVladimir Barinov2013-03-132-0/+30
| | | | | | | | | | | | | | | | | | Add SATA clock for r8a7779 SoC (for both device tree and usual cases). Register SATA controller as a "late" platform device on r8a7779 SoC. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: mach-shmobile: r8a7779: SATA DT configurationVladimir Barinov2013-03-131-0/+7
| | | | | | | | | | | | | | | | | | Allow configuration of the r8a7779 SoC SATA controller using a flattened device tree. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: r8a7779: add Thermal support on DTKuninori Morimoto2013-03-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 76cc1887496fe80138c6b07c37d7f81e4cf27cde (thermal: rcar: add Device Tree support) supported rcar_thermal DT probing. rcar thermal driver doesn't support IRQ on r8a7779 chip since it is using old design IRQ. R-Car/R-Mobile next generation chips are using new design IRQ, and rcar thermal driver is supporting these. This patch adds rcar_thermal DT support for r8a7779 without IRQ. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: tidyup chip series definition order for r8a7740/r8a7779Kuninori Morimoto2013-03-131-2/+1
| | | | | | | | | | | | | | | | move r8a7740_meram_workaround() to r8a7740 area from r8a7779 area Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: r8a7779: use gic_iid macroKuninori Morimoto2013-03-131-12/+12
| | | | | | | | | | | | | | | | | | | | | | "ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID" enabled to use gic_iid macro. This patch exchange current GIC interrupt setting from gic_spi() to gic_iid() Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [ horms+renesas@verge.net.au: Updated git commit id in changelog ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: r8a7779: fixup DT machine nameKuninori Morimoto2013-03-131-1/+1
| | | | | | | | | | | | | | r8a7779 is not sh73a0 Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: r8a7779: fixup dtsi typoKuninori Morimoto2013-03-131-1/+1
| | | | | | | | | | | | | | r8a7779 is not r8a7740 chip Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: add gic_iid macro for ICCIAR / interrupt IDKuninori Morimoto2013-03-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | R-Car H1 datasheet GIC number is indicating GIC ICCIAR / interrupt ID number, not SPI number, but current marzen board code is using gic_spi() with un-understandable calculation. This patch adds new gic_iid() macro which means ICCIAR / interrupt ID, and used the number currently written on datasheet. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [ horms+renesas@verge.net.au: Split board-marzen.c portion into a separate patch ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: mach-shmobile: r8a7740: Add DT names to clock listBastian Hecht2013-03-131-0/+9
| | | | | | | | | | | | | | | | This adds temporarily the alternative device names to the clock list that are used when booting via Device Tree setup. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Remove unused hotplug.cMagnus Damm2013-03-133-75/+0
| | | | | | | | | | | | | | | | | | | | Each CPU Hotplug implementation for mach-shmobile is now self-contained, so this change removes unused helper code in hotplug.c. The two CPU Hotplug capable SoCs sh73a0 and r8a7779 remain unchanged. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Rearrange r8a7779 cpu hotplug codeMagnus Damm2013-03-131-47/+49
| | | | | | | | | | | | | | | | | | Update the r8a7779 SMP code and CPU Hotplug in particular to follow the same style as sh73a0. This means dropping __maybe_unused for #ifdef CONFIG_HOTPLUG_CPU. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Use sh73a0-specific cpu disable codeMagnus Damm2013-03-131-1/+6
| | | | | | | | | | | | | | | | | | | | Convert the sh73a0 CPU Hotplug code to use a local implementation of ->cpu_disable(). With this change in place the sh73a0 SMP code does no longer depend on hotplug.c. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Update r8a7779 to use scu_power_mode()Magnus Damm2013-03-131-27/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the SMP code for R8A7779 to make use of the shared SCU function scu_power_mode() together with the early setup code in shmobile_secondary_vector_scu. With this patch in place the secondary CPUs modify the SCU setting during early boot instead of letting other CPUs deal with the coherency setting before boot. In other words, we used to setup coherency before boot in r8a7779_boot_secondary() but that bit is now instead handled by the code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Update r8a7779 to check SCU for hotplugMagnus Damm2013-03-131-6/+32
| | | | | | | | | | | | | | | | | | | | | | Update the r8a7779 CPU Hotplug code to use SCU PSR to wait for the target CPU core. Previously the shared code in hotplug.c was used to let cpu_kill() wait for cpu_die(). With this change in place the r8a7779 SMP code does not depend on hotplug.c anymore. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Use R8A7779_SCU_BASE with TWDMagnus Damm2013-03-131-4/+3
| | | | | | | | | | | | | | | | Rework the IOMEM() usage for the SCU base address in the case of r8a7779. Adjusts the TWD to use R8A7779_SCU_BASE. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Rework SH73A0_SCU_BASE IOMEM() usageMagnus Damm2013-03-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the IOMEM() usage for the SCU base address in the case of sh73a0. Removes recently introduced build warnings: arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default] arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].start') [enabled by default] arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: initialization makes integer from pointer without a cast [enabled by default] /arch/arm/mach-shmobile/smp-sh73a0.c:45:15: warning: (near initialization for 'twd_local_timer.res[0].end') [enabled by default] Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Fix base address readout in headsmp-scu.SMagnus Damm2013-03-131-1/+2
| | | | | | | | | | | | | | | | | | | | Rework the early SCU setup code in headsmp-scu.S to read the base address in the same way as we use to fetch the address of the invalidation function. Reported-by: Bastian Hecht <hechtb@gmail.com> Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: r8a7779: Remove lan from dtsiSimon Horman2013-03-131-9/+0
| | | | | | | | | | | | | | The ethernet controller is not part of the r8a7779 SoC. Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: r8a7779: Do not initialise i2c as an early deviceSimon Horman2013-03-131-5/+3
| | | | | | | | | | | | | | It is sufficient to initialise i2c as a late device. Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: r8a7779: Do not use early devices with DT referenceSimon Horman2013-03-132-17/+10
| | | | | | | | | | | | | | | | Do not initialise any early devices when using the minimal DT reference code. Only the delay needs to be initialised. Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: sh73a0: Do not use early devices with DT referenceSimon Horman2013-03-132-16/+10
| | | | | | | | | | | | | | | | Do not initialise any early devices when using the minimal DT reference code. Only the delay needs to be initialised. Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: sh73a0: Remove warning about SMPSimon Horman2013-03-131-8/+0
| | | | | | | | | | | | | | | | | | Remove warning about SMP not working with the clock initialisation sheme used for reference DT. This is resolved by not selecting CONFIG_PREEMPT. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: sh73a0: Add smp ops to DT_MACHINE_STARTSimon Horman2013-03-131-0/+1
| | | | | | | | | | | | | | This a board to be brought up with SMP enabled without a board file present. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: sh73a0: Remove sh73a0_init_irq_dt()Simon Horman2013-03-132-9/+2
| | | | | | | | | | | | | | | | | | This is not needed as irq_set_wake is only used for suspend to ram which is not a requirement for bringing up boards using DT. Reported-by: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: sh73a0: fix Z and ZG clock hierarchyGuennadi Liakhovetski2013-03-131-2/+2
| | | | | | | | | | | | | | Z and ZG clocks on sh73a0 have pll0 as their parent, not pll1. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Make EMEV2 setup functions staticMagnus Damm2013-03-131-2/+2
| | | | | | | | | | | | | | | | Adjust emev2_init_delay() and emev2_add_standard_devices_dt() to become static. They are not used outside this file anyway. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Update EMEV2 to use scu_power_mode()Magnus Damm2013-03-131-34/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the SMP code for EMEV2 to make use of the shared SCU function scu_power_mode() together with the early setup code in shmobile_secondary_vector_scu. With this patch in place the secondary CPUs modify the SCU setting during early boot instead of letting other CPUs deal with the coherency setting before boot. In other words, we used to setup coherency before boot in emev2_boot_secondary() but that bit is now instead handled by the code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Common shmobile_scu_base in headsmp-scu.SMagnus Damm2013-03-137-59/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the code in headsmp-scu.S to use a global shmobile_scu_base variable both for convenient SCU base address storage and for the early SCU setup code in shmobile_secondary_vector_scu. With this patch applied r8a7779, sh73a0 and EMEV2 all make use of the global shmobile_scu_base variable. However only sh73a0 makes use of the SCU bring up code in shmobile_secondary_vector_scu. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Move headsmp-sh73a0.S to headsmp-scu.SMagnus Damm2013-03-134-4/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename headsmp-sh73a0.S into headsmp-scu.S and introduce shmobile_secondary_vector_scu(). The goal is to be able to share the function above between all mach-shmobile SoCs that use SCU for SMP. So far only sh73a0 use this. At this time the SCU base address is still hard coded in headsmp-scu.S to 0xf0000000, but this will be changed in the future. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Rework EMEV2 scu_base variableMagnus Damm2013-03-131-7/+8
| | | | | | | | | | | | | | | | | | | | Rename the static scu_base variable into shmobile_scu_base. Later in the series the shmobile_scu_base variable will be made into a global variable so this is preparation only. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Kill off r8a7779 scu_base_addr() functionMagnus Damm2013-03-131-9/+8
| | | | | | | | | | | | | | | | | | | | | | Replace scu_base_addr() with a static shmobile_scu_base variable and introduce R8A7779_SCU_BASE. Later in the series the shmobile_scu_base variable will be made into a global variable so this is preparation only. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: shmobile: Kill off sh73a0 scu_base_addr() functionMagnus Damm2013-03-131-10/+10
| | | | | | | | | | | | | | | | | | | | | | Replace scu_base_addr() with a static shmobile_scu_base variable and introduce SH73A0_SCU_BASE. Later in the series the shmobile_scu_base variable will be made into a global variable so this is preparation only. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * ARM: mach-shmobile: r8a7779: Minimal setup using DTSimon Horman2013-03-133-6/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow a minimal setup of the r8a7779 SoC using a flattened device tree. In particular, configure the i2c and ethernet controllers using a flattened device tree. SCI serial controller and TMU clock source, whose drivers do not yet support configuration using a flattened device tree, are still configured using C code in order to allow booting of a board with this SoC. The ethernet controller also requires a regulator which is a board property. A sample snippet DT for the marzen board is as follows: /dts-v1/; /include/ "r8a7779.dtsi" / { fixedregulator3v3: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; }; &lan0 { vddvario-supply = <&fixedregulator3v3>; vdd33a-supply = <&fixedregulator3v3>; }; Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-04 20:45:11 +0000