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* MIPS: JZ4740: register an irq_domain for the interrupt controllerPaul Burton2015-06-211-0/+6
| | | | | | | | | | | | | | | | When probing the interrupt controller, register an IRQ domain such that the interrupts can be translated by devicetree code & thus used from devicetree. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10140/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DTPaul Burton2015-06-211-1/+6
| | | | | | | | | | | | | | | | Rather than hardcoding the IRQ number used to cascade interrupts from the SoC interrupt controller to the CPU interrupt controller, read that IRQ number from the DT describing the system. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10137/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: probe interrupt controller via DTPaul Burton2015-06-214-5/+18
| | | | | | | | | | | | | | | | | | | | | | Declare the JZ4740 interrupt controller for probe via DT using the standard irqchip_init function, and make use of that function to probe the controller by adding the appropriate node to the JZ4740 dtsi. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Kumar Gala <galak@codeaurora.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10135/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* devicetree: document Ingenic SoC interrupt controller bindingPaul Burton2015-06-211-0/+28
| | | | | | | | | | | | | | | | | | | Add binding documentation for Ingenic SoC interrupt controllers. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Kumar Gala <galak@codeaurora.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: Move arch_init_irq out of arch/mips/jz4740/irq.cPaul Burton2015-06-213-4/+11
| | | | | | | | | | | | | | In preparation for moving the JZ4740 interrupt controller driver to drivers/irqchip, move arch_init_irq into setup.c such that everything remaining in irq.c is related to said JZ4740 interrupt controller. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: use generic plat_irq_dispatchPaul Burton2015-06-211-12/+0
| | | | | | | | | | | | | | Make use of the generic plat_irq_dispatch function introduced by commit 85f7cdacbb81 "MIPS: Provide a generic plat_irq_dispatch", in order to reduce unnecessary code duplication. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10138/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: probe CPU interrupt controller via DTPaul Burton2015-06-212-2/+9
| | | | | | | | | | | | | | | | | | | | | Use the generic irqchip_init function to probe irqchip drivers using DT, and add the appropriate node to the JZ4740 devicetree in place of the call to mips_cpu_irq_init. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris <computersforpeace@gmail.com> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Patchwork: https://patchwork.linux-mips.org/patch/10166/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* IRQCHIP: irq_cpu: declare irqchip table entryPaul Burton2015-06-211-0/+3
| | | | | | | | | | | | | | | | | | | | Allow the MIPS CPU interrupt controller to be probed from DT using the generic __irqchip_of_table for platforms which use irqchip_init. This will avoid such platforms needing to duplicate the compatible string & init function pointer. [ralf@linux-mips.org: Resolved conflict due the preceeding commit that moves irq-cpu.c. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Cc: Felix Fietkau <nbd@openwrt.org> Patchwork: https://patchwork.linux-mips.org/patch/10131/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS/IRQCHIP: Move irq_chip from arch/mips to drivers/irqchip.Ralf Baechle2015-06-2113-56/+57
| | | | | | | While at it, rename it because in drivers/irqchip no longer every CPU is a MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: require & include DTPaul Burton2015-06-216-0/+43
| | | | | | | | | | | | | | | | | | | | Require a DT for JZ4740 based systems, and add a stub one for the qi_lb60 (Ben NanoNote) board. Devices will be migrated to being probed via this DT over time. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Andrew Bresticker <abrestic@chromium.org> Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/10132/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ingenic: Add newer vendor IDsPaul Burton2015-06-212-3/+7
| | | | | | | | | | | | | | | | | | | | | | Ingenic have actually varied the vendor/company ID of the XBurst cores across their range of SoCs, whilst keeping the product ID & revision constant... Add definitions for vendor IDs known to be used in some of Ingenic's newer SoCs, and handle them in the same way as the existing Ingenic vendor ID from the JZ4740. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Co-authored-by: Paul Cercueil <paul@crapouillou.net> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-kernel@vger.kernel.org Cc: Huacai Chen <chenhc@lemote.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/10128/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: JZ4740: introduce CONFIG_MACH_INGENICPaul Burton2015-06-214-9/+13
| | | | | | | | | | | | | | In preparation for supporting Ingenic SoCs other than the JZ4740, introduce MACH_INGENIC to Kconfig & move MACH_JZ4740 to a separate entry selected by the board when appropriate. This allows MACH_INGENIC to be used to enable things generic across Ingenic SoCs. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Andrew Bresticker <abrestic@chromium.org> Patchwork: https://patchwork.linux-mips.org/patch/10130/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* devicetree/bindings: add Qi Hardware vendor prefixPaul Burton2015-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Define a vendor prefix for Qi Hardware, creators of the Ben Nanonote (qi_lb60) among other open devices. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: Hayato Suzuki <hytszk@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: linux-kernel@vger.kernel.org Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Cc: Arnaud Ebalard <arno@natisbad.org> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Antony Pavlov <antonynpavlov@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10142/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* devicetree/bindings: add Ingenic Semiconductor vendor prefixPaul Burton2015-06-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Define a vendor prefix for Ingenic Semiconductor, a vendor of MIPS-based SoCs. Simply use 'ingenic'. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Lars-Peter Clausen <lars@metafoo.de> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: Hayato Suzuki <hytszk@gmail.com> Cc: Thierry Reding <treding@nvidia.com> Cc: linux-kernel@vger.kernel.org Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Cc: Arnaud Ebalard <arno@natisbad.org> Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com> Cc: Antony Pavlov <antonynpavlov@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/10129/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: DEC: Update CPU overridesMaciej W. Rozycki2015-06-211-0/+16
| | | | | | | | | | | | | | | | | | | | | | | Update CPU overrides for the DEC port with the recent additions, shaving off some effectively dead code: text data bss dec hex filename 5586952 233132 5990368 11810452 b43694 vmlinux.32-old 5581248 233140 5990368 11804756 b42054 vmlinux.32-new text data bss dec hex filename 6036936 356648 10756544 17150128 105b0b0 vmlinux.64-old 6029896 360752 10756544 17147192 105a538 vmlinux.64-new The data size increase is due to the special alignment requirement of `init_thread_union' aka `.data..init_task' moving it up to the nearest page boundary and making the amount of padding at its front rely on how far within a page text ends. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10197/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: netlogic: remove unnecessary MTD partition probe specificationBrian Norris2015-06-211-3/+0
| | | | | | | | | | The cmdlinepart parser is already supported in the default probe. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Cc: linux-mtd@lists.infradead.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10071/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: tlb-r3k: Optimise a TLBWI barrier in TLB invalidationMaciej W. Rozycki2015-06-211-2/+2
| | | | | | | | | | | | Replace an explicit barrier with a useful processor instruction in TLB invalidation, following several other such cases elsewhere in `tlb-r3k.c'. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10196/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'Maciej W. Rozycki2015-06-213-7/+8
| | | | | | | | | | | | | | | | | Move the initialisation of the CP0.Wired register implemented by Toshiba TX3922 and TX3927 processors from `tx39_cache_init' to `tlb_init' where it belongs, correcting code structure and making sure initialisation does not rely on `tx39_cache_init' being called before `tlb_init' to work correctly. Make `r3k_have_wired_reg' static as it's no longer externally referred to; remove a stale declaration too. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10195/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: tlb-r3k: Also invalidate wired TLB entries on bootMaciej W. Rozycki2015-06-211-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | Most R3k processor implementations have their 8 first TLB entries fixed as wired, so we always skip them in TLB invalidation. That however means any leftover entries present there at boot will stay throughout the life of the kernel, unless replaced with new ones. So rename `local_flush_tlb_all' to `local_flush_tlb_from' and make it accept the TLB entry to start from. Then use 0 initially at bootstrap, and the first regular entry later on, bypassing any wired entries. Wrap the latter arrangement into a new `local_flush_tlb_all' entry point. There is no need to disable interrupts in the call made from `tlb_init' because it's made before the interrupt subsystem has been initialised; this is also true for secondary processors, should we ever support R3k SMP. So move this piece of code to new `local_flush_tlb_all'. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10194/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: dump_tlb: Take XPA into accountJames Hogan2015-06-211-5/+13
| | | | | | | | | | | | | | | XPA extends the physical addresses on MIPS32, including the EntryLo registers. Update dump_tlb() to concatenate the PFNX field from the high end of the EntryLo registers (as read by mfhc0). The width of physical and virtual addresses are also separated to show only 8 nibbles of virtual but 11 nibbles of physical with XPA. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10077/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: dump_tlb: Take RI/XI bits into accountJames Hogan2015-06-211-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | The RI/XI bits when present are above the PFN field in the EntryLo registers, at bits 63,62 when read with dmfc0, and bits 31,30 when read with mfc0. This makes them appear as part of the physical address, since the other bits are masked with PAGE_MASK, for example: Index: 253 pgmask=16kb va=77b18000 asid=75 [pa=1000744000 c=5 d=1 v=1 g=0] [pa=100134c000 c=5 d=1 v=1 g=0] The physical addresses have bit 36 set, which corresponds to bit 30 of EntryLo1, the XI bit. Explicitly mask off the RI and XI bits from the printed physical address, and print the RI and XI bits separately if they exist, giving output more like this: Index: 226 pgmask=16kb va=77be0000 asid=79 [ri=0 xi=1 pa=01288000 c=5 d=1 v=1 g=0] [ri=0 xi=0 pa=010e4000 c=5 d=0 v=1 g=0] Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: David Daney <ddaney@caviumnetworks.com> Patchwork: https://patchwork.linux-mips.org/patch/10080/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: dump_tlb: Take EHINV bit into accountJames Hogan2015-06-211-0/+3
| | | | | | | | | | | | | | | | The EHINV bit in EntryHi allows a TLB entry to be properly marked invalid so that EntryHi doesn't have to be set to a unique value to avoid machine check exceptions due to multiple matching entries. Unfortunately dump_tlb() doesn't take this into account so it will print all the uninteresting invalid TLB entries if the current ASID happens to be 00. Therefore add a condition to skip entries which are marked invalid with the EHINV bit. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10076/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: dump_tlb: Take global bit into accountJames Hogan2015-06-212-3/+12
| | | | | | | | | | | | | | The TLB only matches the ASID when the global bit isn't set, so dump_tlb() shouldn't really be skipping global entries just because the ASID doesn't match. Fix the condition to read the TLB entry's global bit from EntryLo0. Note that after a TLB read the global bits in both EntryLo registers reflect the same global bit in the TLB entry. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10079/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: dump_tlb: Make use of EntryLo bit definitionsJames Hogan2015-06-212-12/+12
| | | | | | | | | | | Make use of recently added EntryLo bit definitions in mipsregs.h when dumping TLB contents. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10075/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: dump_tlb: Refactor TLB matchingJames Hogan2015-06-211-30/+35
| | | | | | | | | | | | Refactor the TLB matching code in dump_tlb() slightly so that the conditions which can cause a TLB entry to be skipped can be more easily extended. This should prevent the match condition getting unwieldy once it is updated to take further conditions into account. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10081/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: dump_tlb: Use tlbr hazard macrosJames Hogan2015-06-211-8/+3
| | | | | | | | | | | | | | | Use the new tlb read hazard macros from <asm/hazards.h> rather than the local BARRIER() macro which uses 7 ops regardless of the kernel configuration. We use mtc0_tlbr_hazard for the hazard between mtc0 to the index register and the tlbr, and tlb_read_hazard for the hazard between the tlbr and the mfc0 of the TLB registers written by tlbr. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10074/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: mipsregs.h: Add EntryLo bit definitionsJames Hogan2015-06-211-0/+22
| | | | | | | | | | | | | | Add definitions for EntryLo register bits in mipsregs.h. The R4000 compatible ones are prefixed MIPS_ENTRYLO_ and the R3000 compatible ones are prefixed R3K_ENTRYLO_. These will be used in later patches. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/10073/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: hazards: Add hazard macros for tlb readJames Hogan2015-06-211-0/+52
| | | | | | | | | | | | | | | | | | | | | | Add hazard macros to <asm/hazards.h> for the following hazards around tlbr (TLB read) instructions, which are used in TLB dumping code and some KVM TLB management code: - mtc0_tlbr_hazard Between mtc0 (Index) and tlbr. This is copied from mtc0_tlbw_hazard in all cases on the assumption that tlbr always has similar data user timings to tlbw. - tlb_read_hazard Between tlbr and mfc0 (various TLB registers). This is copied from tlbw_use_hazard in all cases on the assumption that tlbr has similar data writer characteristics to tlbw, and mfc0 has similar data user characteristics to loads and stores. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10078/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add SysRq operation to dump TLBs on all CPUsJames Hogan2015-06-213-0/+79
| | | | | | | | | | Add a MIPS specific SysRq operation to dump the TLB entries on all CPUs, using the 'x' trigger key. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10072/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: traps: print Exception Code in __show_regs()Petri Gynther2015-06-211-3/+4
| | | | | | | | | Print Exception Code when printing the Cause register. Signed-off-by: Petri Gynther <pgynther@google.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9998/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47xx: Read board info for all bcma busesRafał Miłecki2015-06-213-29/+22
| | | | | | | | | | | | | | | | | | Extra bcma buses may be totally different models, see following dump: boardtype=0x0646 pci/1/1/boardtype=0x0545 pci/2/1/boardtype=0x62b We need to detect them properly to allow drivers apply some board specific hacks. [ralf@linux-mips.org: folded in Rafal's fix.] Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/10028/ Patchwork: https://patchwork.linux-mips.org/patch/10048/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47xx: Extract info about et2 interfaceRafał Miłecki2015-06-212-0/+9
| | | | | | | | | | | | | New devices may have more than 1 Ethernet core (device). We should extract info about them to make it available to Ethernet drivers. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Hante Meuleman <meuleman@broadcom.com> Cc: Ian Kent <raven@themaw.net> Patchwork: https://patchwork.linux-mips.org/patch/10027/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47xx: Extract all boardflags to new u32 fieldsRafał Miłecki2015-06-212-1/+7
| | | | | | | | | | | | | For years we planned to get rid of old u16 fields, let's start doing it with MIPS code. This process will take some time, it requires doing the same in ssb/bcma and then switching all drivers to new fields. This will be handled in separated patches submitted to appropriate trees. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/10026/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Simplify function looking for NVRAM entryRafał Miłecki2015-06-211-8/+5
| | | | | | | | | | | | | | | First of all it shouldn't modify copied NVRAM just to make sure it can loop over all entries. It's enough to just compare current position pointer with the end of buffer address. Secondly buffer is guaranteed to be \0 ended, so we don't need strnchr. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Hante Meuleman <meuleman@broadcom.com> Cc: Ian Kent <raven@themaw.net> Patchwork: https://patchwork.linux-mips.org/patch/10032/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Make sure NVRAM buffer ends with \0Rafał Miłecki2015-06-211-4/+5
| | | | | | | | | | | | This will simplify reading its contents. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Cc: Hante Meuleman <meuleman@broadcom.com> Cc: Ian Kent <raven@themaw.net> Patchwork: https://patchwork.linux-mips.org/patch/10031/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Malta: Make maltasmvp_defconfig useful again.Ralf Baechle2015-06-211-9/+8
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ftrace: Enable support for syscall tracepoints.Ralf Baechle2015-06-211-0/+1
| | | | | | | All the necessary support code is already there so all that's left is to enable the feature in kconfig. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Linux 4.1-rc8v4.1-rc8Linus Torvalds2015-06-141-1/+1
|
* Merge branch 'fixes' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2015-06-142-93/+144
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine fixes from Vinod Koul: "Here are hopefully last set of fixes for 4.1. This time we have: - fixing pause capability reporting on both dmaengine pause & resume support by Krzysztof - locking fix fir at_xdmac by Ludovic - slave configuration fix for at_xdmac by Ludovic" * 'fixes' of git://git.infradead.org/users/vkoul/slave-dma: dmaengine: Fix choppy sound because of unimplemented resume dmaengine: at_xdmac: rework slave configuration part dmaengine: at_xdmac: lock fixes
| * dmaengine: Fix choppy sound because of unimplemented resumeKrzysztof Kozlowski2015-06-121-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some drivers implement only pause operation (no resuming). Example is pl330 where pause is needed for getting residuum. pl330 does not support resume operation, transfer must be stopped after pause. However for slaves this is exposed always as "pause and resume" which introduces subtle errors on Odroid U3 board (Exynos4412 with pl330). After adding pause function to pl330 driver the audio playback (utilizing DMA) gets choppy after some time (approximately 24 hours). Fix this by exposing "cmd_pause" if and only if pause and resume are implemented. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reported-by: gabriel@unseen.is Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Cc: <stable@vger.kernel.org> Fixes: 88987d2c7534 ("dmaengine: pl330: add DMA_PAUSE feature") Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_xdmac: rework slave configuration partLudovic Desroches2015-06-081-60/+96
| | | | | | | | | | | | | | | | | | | | | | | | Rework slave configuration part in order to more report wrong errors about the configuration. Only maxburst and addr width values are checked when doing the slave configuration. The validity of the channel configuration is done at prepare time. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Cc: stable@vger.kernel.org # 4.0 and later Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: at_xdmac: lock fixesLudovic Desroches2015-06-081-32/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using _bh variant for spin locks causes this kind of warning: Starting logging: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 3 at /ssd_drive/linux/kernel/softirq.c:151 __local_bh_enable_ip+0xe8/0xf4() Modules linked in: CPU: 0 PID: 3 Comm: ksoftirqd/0 Not tainted 4.1.0-rc2+ #94 Hardware name: Atmel SAMA5 [<c0013c04>] (unwind_backtrace) from [<c00118a4>] (show_stack+0x10/0x14) [<c00118a4>] (show_stack) from [<c001bbcc>] (warn_slowpath_common+0x80/0xac) [<c001bbcc>] (warn_slowpath_common) from [<c001bc14>] (warn_slowpath_null+0x1c/0x24) [<c001bc14>] (warn_slowpath_null) from [<c001e28c>] (__local_bh_enable_ip+0xe8/0xf4) [<c001e28c>] (__local_bh_enable_ip) from [<c01fdbd0>] (at_xdmac_device_terminate_all+0xf4/0x100) [<c01fdbd0>] (at_xdmac_device_terminate_all) from [<c02221a4>] (atmel_complete_tx_dma+0x34/0xf4) [<c02221a4>] (atmel_complete_tx_dma) from [<c01fe4ac>] (at_xdmac_tasklet+0x14c/0x1ac) [<c01fe4ac>] (at_xdmac_tasklet) from [<c001de58>] (tasklet_action+0x68/0xb4) [<c001de58>] (tasklet_action) from [<c001dfdc>] (__do_softirq+0xfc/0x238) [<c001dfdc>] (__do_softirq) from [<c001e140>] (run_ksoftirqd+0x28/0x34) [<c001e140>] (run_ksoftirqd) from [<c0033a3c>] (smpboot_thread_fn+0x138/0x18c) [<c0033a3c>] (smpboot_thread_fn) from [<c0030e7c>] (kthread+0xdc/0xf0) [<c0030e7c>] (kthread) from [<c000f480>] (ret_from_fork+0x14/0x34) ---[ end trace b57b14a99c1d8812 ]--- It comes from the fact that devices can called some code from the DMA controller with irq disabled. _bh variant is not intended to be used in this case since it can enable irqs. Switch to irqsave/irqrestore variant to avoid this situation. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Cc: stable@vger.kernel.org # 4.0 and later Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | Merge tag 'ntb-4.1' of git://github.com/jonmason/ntbLinus Torvalds2015-06-141-1/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull NTB fixes from Jon Mason: "I apologize for the tardiness of this request. Here are a couple of last minute NTB bug fixes for v4.1: NTB bug fixes to address issues in unmapping the MW reg base and vbase, and an uninitialized variable on Atom platforms" * tag 'ntb-4.1' of git://github.com/jonmason/ntb: ntb: initialize max_mw for Atom before using it ntb: iounmap MW reg and vbase in error path
| * | ntb: initialize max_mw for Atom before using itDaniel Verkamp2015-06-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ab760a0 (ntb: Adding split BAR support for Haswell platforms) changed ntb_device's mw from a fixed-size array into a pointer that is allocated based on limits.max_mw; however, on Atom platforms, max_mw is not initialized until ntb_device_setup(), which happens after the allocation. Fill out max_mw in ntb_atom_detect() to match ntb_xeon_detect(); this happens before the use of max_mw in the ndev->mw allocation. Fixes a null pointer dereference on Atom platforms with ntb hardware. v2: fix typo (mw_max should be max_mw) Signed-off-by: Daniel Verkamp <daniel.verkamp@intel.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * | ntb: iounmap MW reg and vbase in error pathJon Mason2015-06-081-1/+1
| |/ | | | | | | | | | | | | | | | | The MW regbase and vbase(s) were not being freed if an error occurred in the vbase allocation loop. This is corrected by updating the error path for the allocation loop to err4. Reported-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-06-147-25/+29
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull more MIPS fixes from Ralf Baechle: "Another round of 4.1 MIPS fixes, one fix to a MIPS-specific #if condition in lib/mpi, one fix to the MIPS GIC irqchip driver and one SSB fix. Details: - fix handling of clock in chipco SSB driver. - fix two MIPS-specific #if conditions to correctly work for GCC 5.1. - fix damage to R6 pgtable bits done by XPA support. - fix possible crash due to unloading modules that contain statically defined platform devices. - fix disabling of the MSA ASE on context switch to also work correctly when a new thread/process has the CPU for the very first time. This is part of linux-next and has been beaten to death on Imagination's test farm. While things are not looking too grim this pull request also means the rate of fixes for 4.1 remains nearly constant so I'd not be unhappy if you'd delay the release" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: MPI: MIPS: Fix compilation error with GCC 5.1 IRQCHIP: mips-gic: Don't nest calls to do_IRQ() MIPS: MSA: bugfix - disable MSA correctly for new threads/processes. MIPS: Loongson: Do not register 8250 platform device from module. MIPS: Cobalt: Do not build MTD platform device registration code as module. SSB: Fix handling of ssb_pmu_get_alp_clock() MIPS: pgtable-bits: Fix XPA damage to R6 definitions.
| * | MPI: MIPS: Fix compilation error with GCC 5.1Jaedon Shin2015-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes mips compilation error: lib/mpi/generic_mpih-mul1.c: In function 'mpihelp_mul_1': lib/mpi/longlong.h:651:2: error: impossible constraint in 'asm' Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/10546/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | IRQCHIP: mips-gic: Don't nest calls to do_IRQ()Rabin Vincent2015-06-131-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GIC chained handlers use do_IRQ() to call the subhandlers. This means that irq_enter() calls get nested, which leads to preempt count looking like we're in nested interrupts, which in turn leads to all system time being accounted as IRQ time in account_system_time(). Fix it by using generic_handle_irq(). Since these same functions are used in some systems (if cpu_has_veic) from a low-level vectored interrupt handler which does not go throught do_IRQ(), we need to do it conditionally. Signed-off-by: Rabin Vincent <rabin.vincent@axis.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: linux-mips@linux-mips.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Patchwork: https://patchwork.linux-mips.org/patch/10545/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: MSA: bugfix - disable MSA correctly for new threads/processes.Ralf Baechle2015-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Due to the slightly odd way that new threads and processes start execution when scheduled for the very first time they were bypassing the required disable_msa call. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Loongson: Do not register 8250 platform device from module.Ralf Baechle2015-06-101-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_SERIAL_8250 is set to m, the Loongson seria.ko module might get unloaded while the serial driver modules are still loaded resulting in stale references to the destroyed platform_device instance. Anyway, platform devices should always be registered indicated what devices are present, _not_ what drivers have been configured. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Reported-by: Paul Gortmaker <paul.gortmaker@windriver.com> Patchwork: https://patchwork.linux-mips.org/patch/10538/
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