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* clk/exynos5420: add gate clock for mixer sysmmuRahul Sharma2013-08-292-1/+3
| | | | | | | | Adding sysmmu clock for mixer for exynos5420. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk/exynos5420: add sclk_hdmiphy to the list of special clocksRahul Sharma2013-08-292-2/+3
| | | | | | | | | Add sclk_hdmiphy to the list of exposed clocks. This is required by hdmi driver to change the parent of hdmi clock. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: wm831x: Provide is_prepared() rather than is_enabled()Mark Brown2013-08-291-7/+7
| | | | | | | | | Since the driver was written an is_prepared() operation has been made possible. Since the driver uses I2C I/O only prepare operations are provided so move the is_enabled() operation over to is_prepared(). Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystemRahul Sharma2013-08-281-2/+2
| | | | | | | | | parent of hdmi and mixer block is mentioned as aclk200 which is not correct. It is clocked by the ouput of aclk200_disp1. Hence parent for mixer and hdmi clocks is changed to aclk200_disp1. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra30: Don't wait for PLL_U lock bitTuomas Tynkkynen2013-08-281-1/+1
| | | | | | | | | | | The lock bit on PLL_U does not seem to be working correctly and sometimes never gets set when waiting for the PLL to come up. Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: s3c64xx: Fix incorrect placement of __initdataSachin Kamat2013-08-271-2/+2
| | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sunxi: Fix incorrect placement of __initconstSachin Kamat2013-08-271-30/+30
| | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: refreshed patch based on sunxi changes]
* clk: kirkwood: Fix incorrect placement of __initconstSachin Kamat2013-08-271-7/+7
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: dove: Fix incorrect placement of __initconstSachin Kamat2013-08-271-6/+6
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: armada-xp: Fix incorrect placement of __initconstSachin Kamat2013-08-271-6/+6
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: armada-370: Fix incorrect placement of __initconstSachin Kamat2013-08-271-7/+7
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Gregory Clement <gregory.clement@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: u300: Fix incorrect placement of __initconstSachin Kamat2013-08-271-2/+2
| | | | | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. While at it also make 'u300_clk_lookup' static as it is used only in this file. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: nomadik: Fix incorrect placement of __initconstSachin Kamat2013-08-271-2/+2
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: bcm2835: Fix incorrect placement of __initconstSachin Kamat2013-08-271-1/+1
| | | | | | | | | __initconst should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge tag 'sunxi-clk-for-3.12' of https://github.com/mripard/linux into ↵Mike Turquette2013-08-275-38/+462
|\ | | | | | | | | | | | | | | | | | | | | | | clk-next-sunxi Allwinner clock changes for 3.12 These patches mostly do some cleanup to introduce the basic gated clocks for the Allwinner A10s, A20 and A31 SoCs. Conflicts: drivers/clk/sunxi/clk-sunxi.c
| * clk: sunxi: Add Allwinner A20 gatesMaxime Ripard2013-08-263-0/+116
| | | | | | | | | | | | | | | | | | | | | | The Allwinner A20 is almost identical to the earlier A10 SoC from Allwinner on many aspects, including the clocks tree. However, since the A20 has some additionnal IPs compared to the A10, the clock tree isn't exactly the same, especially when it comes to the gated clocks available. We thus need to register different clock gates for the A20. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
| * clk: sunxi: Add A31 clocks supportMaxime Ripard2013-08-263-0/+213
| | | | | | | | | | | | | | | | | | | | | | The A31 has a mostly different clock set compared to the other older SoCs currently supported in the Allwinner clock driver. Add support for the basic useful clocks. The other ones will come in eventually. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
| * clk: sunxi: Allow to specify the divider width from the dividers dataMaxime Ripard2013-08-261-11/+13
| | | | | | | | | | | | | | | | | | The divider width used to be hardcoded. Some A31 dividers are no longer with the hardcoded width, so we need to make it specific to each divider and set it in the dividers data. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
| * clk: sunxi: Rename the structure to prepare the addition of sun6iMaxime Ripard2013-08-261-27/+27
| | | | | | | | | | | | | | | | Rename all the generic-named structure to sun4i to avoid confusion when we will introduce the sun6i (A31) clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Emilio López <emilio@elopez.com.ar>
| * clk: sunxi: fix initialization of basic clocksEmilio López2013-08-261-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Mike Turquette <mturquette@linaro.org>
| * clk: sunxi: Add A10s gatesMaxime Ripard2013-08-263-0/+93
| | | | | | | | | | | | | | | | | | The Allwinner A10s has a slightly different gates set than the A10 and A13, so add these gates to the clk driver. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar> Reviewed-by: Emilio López <emilio@elopez.com.ar>
* | clk: wrap I/O access for improved portabilityGerhard Sittig2013-08-274-9/+26
| | | | | | | | | | | | | | | | | | | | | | the common clock drivers were motivated/initiated by ARM development and apparently assume little endian peripherals wrap register/peripherals access in the common code (div, gate, mux) in preparation of adding COMMON_CLK support for other platforms Signed-off-by: Gerhard Sittig <gsi@denx.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge branch 'clk-next-s3c64xx-delta' into clk-nextMike Turquette2013-08-272-98/+13
|\ \
| * | clk: samsung: pll: Use new registration method for PLL6552 and PLL6553Tomasz Figa2013-08-262-98/+13
| | | | | | | | | | | | | | | | | | | | | | | | This patch modifies PLL6552 and PLL6553 clock drivers to use recently added common Samsung PLL registration method. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: get matching entry under lock in of_clk_init()Alex Elder2013-08-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently of_clk_init() finds a matching device node while holding the device tree spinlock. When a matching device node is found, the lock is dropped and then re-acquired in order to get a reference to the matching device id structure. Acquiring the spinlock twice is unnecessary (and it opens a vulnerable window that could conceivably lead to errors). There already exists an interface for both finding and taking a reference to a device id under lock, so use it. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: sunxi: fix initialization of basic clocksEmilio López2013-08-271-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the recent move towards CLK_OF_DECLARE(...), the driver stopped initializing osc32k, which is compatible "fixed-clock". This is because we never called of_clk_init(NULL). Fix this by moving the only other simple clock (osc24M) to use CLK_OF_DECLARE(...) and call of_clk_init(NULL) to initialize both of them. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: mvebu: add missing iounmapJisheng Zhang2013-08-232-7/+15
| | | | | | | | | | | | | | | | | | | | | Add missing iounmap to setup error path. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: handle NULL struct clk gracefullyMike Turquette2013-08-211-1/+7
| |/ |/| | | | | | | | | | | | | | | | | At some point changes to clk_set_rate and clk_set_parent introduced a bug whereby NULL struct clk pointers were treated as an error. This is in violation of the API in include/linux/clk.h. Reintroduce graceful handling of NULL clk's by bailing from clk_set_rate and clk_set_parent with return codes of zero. Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge tag 'zynq-clk-for-3.12' of git://git.xilinx.com/linux-xlnx into clk-nextMike Turquette2013-08-201-5/+14
|\ \ | | | | | | | | | | | | | | | | | | | | | arm: Xilinx Zynq clock changes for v3.12 Just small two changes where the first fixes documentation and the second improves code readability.
| * | clk/zynq/pll: Use #defines for fbdiv min/max valuesSoren Brinkmann2013-08-201-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | Use more descriptive #defines for the minimum and maximum PLL feedback divider. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | clk/zynq/pll: Fix documentation for PLL register functionSoren Brinkmann2013-08-201-1/+7
| | | | | | | | | | | | | | | Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | clk: clk-mux: implement remuxing on set_rateJames Hogan2013-08-193-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement clk-mux remuxing if the CLK_SET_RATE_NO_REPARENT flag isn't set. This implements determine_rate for clk-mux to propagate to each parent and to choose the best one (like clk-divider this chooses the parent which provides the fastest rate <= the requested rate). The determine_rate op is implemented as a core helper function so that it can be easily used by more complex clocks which incorporate muxes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: add CLK_SET_RATE_NO_REPARENT flagJames Hogan2013-08-1918-276/+388
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a CLK_SET_RATE_NO_REPARENT clock flag, which will prevent muxes being reparented during clk_set_rate. To avoid breaking existing platforms, all callers of clk_register_mux() are adjusted to pass the new flag. Platform maintainers are encouraged to remove the flag if they wish to allow mux reparenting on set_rate. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Haojian Zhuang <haojian.zhuang@linaro.org> Cc: Chao Xie <xiechao.mail@gmail.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Emilio López" <emilio@elopez.com.ar> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Andrew Chew <achew@nvidia.com> Cc: Doug Anderson <dianders@chromium.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Cc: Tomasz Figa <t.figa@samsung.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: spear-devel@list.st.com Cc: linux-tegra@vger.kernel.org Tested-by: Haojian Zhuang <haojian.zhuang@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> [tegra] Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> [sunxi] Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> [Zynq] Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: add support for clock reparent on set_rateJames Hogan2013-08-194-66/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add core support to allow clock implementations to select the best parent clock when rounding a rate, e.g. the one which can provide the closest clock rate to that requested. This is by way of adding a new clock op, determine_rate(), which is like round_rate() but has an extra parameter to allow the clock implementation to optionally select a different parent clock. The core then takes care of reparenting the clock when setting the rate. The parent change takes place with the help of some new private data members. struct clk::new_parent specifies a clock's new parent (NULL indicates no change), and struct clk::new_child specifies a clock's new child (whose new_parent member points back to it). The purpose of these are to allow correct walking of the future tree for notifications prior to actually reparenting any clocks, specifically to skip child clocks who are being reparented to another clock (they will be notified via the new parent), and to include any new child clock. These pointers are set by clk_calc_subtree(), and the new_child pointer gets cleared when a child is actually reparented to avoid duplicate POST_RATE_CHANGE notifications. Each place where round_rate() is called, determine_rate() is checked first and called in preference. This restructures a few of the call sites to simplify the logic into if/else blocks. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: move some parent related functions upwardsJames Hogan2013-08-191-104/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move some parent related functions up in clk.c so they can be used by the modifications in the following patch which enables clock reparenting during set_rate. No other changes are made so this patch makes no functional difference in isolation. This is separate from the following patch primarily to ease readability of that patch. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: abstract parent cacheJames Hogan2013-08-192-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Abstract access to the clock parent cache by defining clk_get_parent_by_index(clk, index). This allows access to parent clocks from clock drivers. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: export fixed-factor, gate & mux registrationMike Turquette2013-08-163-0/+5
| | | | | | | | | | | | | | | | | | These registration calls may be used by loadable modules. Export them. Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: clk-divider: Export clk_register_divider()Fabio Estevam2013-08-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_register_divider() needs to be exported so that it could be used in a module driver, otherwise we get the following error: ERROR: "clk_register_divider" [sound/soc/mxs/snd-soc-mxs.ko] undefined! Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: also export clk_register_divider_table]
* | | clk: fixed-rate: Export clk_fixed_rate_register()Stephen Boyd2013-08-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Export this symbol so that modules can register fixed rate clocks. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: prima2: Fix incorrect placement of __initdataSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: tegra30: Fix incorrect placement of __initdataSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: tegra20: Fix incorrect placement of __initdataSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: tegra114: Fix incorrect placement of __initdataSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: exynos5440: Fix incorrect placement of __initdataSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: exynos5420: Fix incorrect placement of __initdataSachin Kamat2013-08-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: exynos5250: Fix incorrect placement of __initdataSachin Kamat2013-08-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: exynos4: Fix incorrect placement of __initdataSachin Kamat2013-08-081-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | __initdata should be placed between the variable name and equal sign for the variable to be placed in the intended section. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: s2mps11: Add support for s2mps11Yadwinder Singh Brar2013-08-083-0/+280
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to register three(AP/CP/BT) buffered 32.768 KHz outputs of mfd-s2mps11 with common clock framework. Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: exynos5420: Make exynos5420_plls staticSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | 'exynos5420_plls' is used only in this file. Make is static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | | clk: exynos5250: Make exynos5250_plls staticSachin Kamat2013-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | exynos5250_plls is used only in this file. Make it static. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-01 01:09:21 +0000