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* MIPS: lantiq: copy the commandline from the devicetreeJohn Crispin2014-11-241-0/+2
| | | | | | | | | | | | | | This is a regression caused by: commit afb46f7996e91aeb36e07bc92cf96e8045bec00e Author: Rob Herring <robh@kernel.org> Date: Wed Apr 2 19:07:24 2014 -0500 mips: ralink: convert to use unflatten_and_copy_device_tree Make the of init code reuse the cmdline defined inside the dts. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8048/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: move eiu init after irq_domain registerJohn Crispin2014-11-241-24/+24
| | | | | | | | The eiu init failed as the irq_domain was not yet available. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8047/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: export soc typeJohn Crispin2014-11-242-0/+7
| | | | | | | | The voice and dsl drivers need to know which SoC we are running on. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/8046/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: add support for xrx200 firmware depending on soc typeJohn Crispin2014-11-241-1/+22
| | | | | | | | | | | | VR9 needs different firmware files for the various phy/soc revisions. Some boards are ship with older and newer SoC revisions. To be able to boot a single image on all versions we need to define both firmware files inside the devicetree. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8045/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: reboot gphy on restartJohn Crispin2014-11-241-1/+8
| | | | | | | | | A reboot sometimes lead to a none working phy. An explicit reboot fixes the problem. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8044/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: add reset-controller api supportJohn Crispin2014-11-242-0/+63
| | | | | | | | | Add a reset-controller binding for the reset registers found on the lantiq SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8043/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: handle vmmc memory reservationJohn Crispin2014-11-242-0/+71
| | | | | | | | | | The Lantiq SoCs have a 2nd mips core called "voice mips macro core (vmmc)" which is used to run the voice firmware. This driver allows us to register a chunk of memory that the voice driver can later use for the 2nd core. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/8042/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Alchemy: Remove direct access to prepare_count field of struct clkTomeu Vizoso2014-11-241-4/+3
| | | | | | | | | | | | | | | Replacing it with a call to __clk_is_prepared(), which isn't entirely equivalent but in practice shouldn't matter. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Manuel Lauss <manuel.lauss@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8120/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic: Bump up rating of GIC timerAndrew Bresticker2014-11-241-1/+1
| | | | | | | | | | | | | | | | | Bump up the rating of the GIC timer so that it gets prioritized over the CP0 timer. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8141/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic: Use clockevents_config_and_registerAndrew Bresticker2014-11-241-9/+1
| | | | | | | | | | | | | | | | | Use clockevents_config_and_register to setup the clock_event_device based on frequency and min/max ticks instead of doing it ourselves. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8140/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic: Use CPU notifiers to setup the timerAndrew Bresticker2014-11-242-20/+45
| | | | | | | | | | | | | | | | | | Instead of requiring an explicit call to gic_clockevent_init in the SMP startup path, use CPU notifiers to register and enable the GIC timer on CPU startup. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8139/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic: Use percpu_dev_idAndrew Bresticker2014-11-241-3/+2
| | | | | | | | | | | | | | | | | Since the GIC timer IRQ is a percpu IRQ, we can use percpu_dev_id to pass the IRQ handler the correct clock_event_device. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8138/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic: Remove gic_event_handlerAndrew Bresticker2014-11-241-5/+0
| | | | | | | | | | | | | | | | Remove gic_event_handler since it is completely unnecessary. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic: Move gic_frequency to clocksource driverAndrew Bresticker2014-11-244-2/+5
| | | | | | | | | | | | | | | | | | There's no reason for gic_frequency to be global any more and it certainly doesn't belong in the GIC irqchip driver, so move it to the GIC clocksource driver. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8137/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic: Staticize local symbolsAndrew Bresticker2014-11-241-5/+5
| | | | | | | | | | | | | | | | | There are a number of variables and functions which are unnecessarily global. Mark them static. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8135/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clocksource: mips-gic: Combine with GIC clockevent driverAndrew Bresticker2014-11-246-119/+92
| | | | | | | | | | | | | | | | | | | Combine the GIC clocksource driver with the GIC clockevent driver from arch/mips/kernel/cevt-gic.c and remove the clockevent driver's separate Kconfig symbol. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8132/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move GIC clocksource driver to drivers/clocksource/Andrew Bresticker2014-11-247-9/+9
| | | | | | | | | | | | | | | | Move the GIC clocksource driver to drivers/clocksource/mips-gic-timer.c. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8133/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Use GIC_SH_WEDGE_{SET,CLR} macrosAndrew Bresticker2014-11-241-2/+2
| | | | | | | | | | | | | | | | Use the GIC_SH_WEDGE_{SET,CLR} macros provided by mips-gic.h. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Remove gic_{pending,itrmask}_regsAndrew Bresticker2014-11-241-13/+3
| | | | | | | | | | | | | | | | | | There's no reason for the pending and masked interrupt bitmasks to be global. Just declare them on the stack in gic_get_int() since they only consume (256*2)/8 = 64 bytes. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8131/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Clean up #includesAndrew Bresticker2014-11-241-5/+2
| | | | | | | | | | | | | | | | Sort the #includes and remove those which are unnecessary. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8130/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* irqchip: mips-gic: Clean up header fileAndrew Bresticker2014-11-242-104/+29
| | | | | | | | | | | | | | | | | Remove duplicate #defines and unnecessary #includes, fix parenthesization, and re-order register definitions in ascending order. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8128/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MAINTAINERS: Add entry for bcm63xx/bcm33xx UDC gadget driverKevin Cernekee2014-11-241-0/+6
| | | | | | | | | | | | | | | This hardware shows up on the newly-supported BCM3384 cable chip, as well as several old BCM63xx DSL chips. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8172/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MAINTAINERS: Add entry for BCM33xx cable chipsKevin Cernekee2014-11-241-0/+8
| | | | | | | | | | | | | | Add myself as a maintainer for the new BCM3384 board support code. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8171/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: bcm3384: Initial commit of bcm3384 platform supportKevin Cernekee2014-11-2413-0/+698
| | | | | | | | | | | | | | | | | | | | | | | | | | | This supports SMP Linux running on the BCM3384 Zephyr (BMIPS5000) application processor, with fully functional UART and USB 1.1/2.0. Device Tree is used to configure the following items: - All peripherals - Early console base address - SMP or UP mode - MIPS counter frequency - Memory size / regions - DMA offset - Kernel command line The DT-enabled bootloader and build instructions are posted at https://github.com/Broadcom/aeolus Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8170/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Documentation: DT: Add "mti" vendor prefixKevin Cernekee2014-11-241-0/+1
| | | | | | | | | | | | | | | We have a bunch of platforms using "mti,cpu-interrupt-controller" but the "mti" prefix isn't documented. Fix this. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8169/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Documentation: DT: Add entries for BCM3384 and its peripheralsKevin Cernekee2014-11-244-0/+67
| | | | | | | | | | | | | | This covers the new "brcm,*" devices added in the upcoming bcm3384 commit. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8168/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Create a helper function for DT setupKevin Cernekee2014-11-244-22/+22
| | | | | | | | | | | | | | | A couple of platforms register two buses and call of_platform_populate(). Move this into a common function to reduce duplication. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8167/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)Kevin Cernekee2014-11-242-0/+2
| | | | | | | | | | | | | | | | This is a dual core (quad thread) BMIPS5000. It needs a little extra code to boot the second core (CPU2/CPU3), but for now we can treat it the same as a single core BMIPS5000. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8166/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Add special cache handling in c-r4k.cKevin Cernekee2014-11-241-0/+43
| | | | | | | | | | | | | | | | | | | BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit, so it isn't necessary to raise IPIs to keep both CPUs coherent. BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$ fills from D$. But a special sequence with 2 SYNCs and 32 NOPs is needed to ensure coherency. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8165/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Let each platform customize the CPU1 IRQ maskKevin Cernekee2014-11-242-2/+5
| | | | | | | | | | | | | | | | On some chips like bcm3384, "other stuff" gets wired up to CPU1's IE_IRQ1 input, generating spurious IRQs. In this case we want the platform code to be able to mask it off. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8163/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUsKevin Cernekee2014-11-241-0/+2
| | | | | | | | | | | | | | | | BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2 line size. If L1_CACHE_SHIFT is undersized, DMA buffers will not be cacheline-aligned and terrible things will happen. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8164/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Allow MIPS_CPU_SCACHE to be used with different line sizesKevin Cernekee2014-11-241-1/+1
| | | | | | | | | | | | | | | | | CONFIG_MIPS_CPU_SCACHE determines whether to build sc-mips.c. However, it is currently hardwired to use an L1_SHIFT of 6 (64 bytes). Move the L1_SHIFT selection into the CPU or SoC section so that other SoCs can select different values. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8162/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Explicitly configure reset vectors prior to secondary bootKevin Cernekee2014-11-241-21/+8
| | | | | | | | | | | | | | | | | The secondary CPU's reset vector needs to be set to KSEG1 for a cold boot (release from reset), or KSEG0 for a warm restart. On a cold boot KSEG0 may be unavailable (BMIPS4380), and on a warm restart KSEG1 may be unavailable (XKS01 mode on 4380 or 5000). Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Mask off timer IRQs when hot-unplugging a CPUJon Fraser2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU interrupts need to be disabled on a cpu being taken down. When a cpu is hot-plugged out of the system the following sequence occurs. On the CPU where the hotplug sequence was initiated: cpu_down _cpu_down { __cpu_notify(CPU_DOWN_PREPARE __stop_machine(take_cpu_down wait for cpu to run disable code. __cpu_die } On the CPU being disabled: take_cpu_down __cpu_disable { mp_ops->cpu_disable bmips_cpu_disable clear_c0_status(IE_IRQ5) (added) cpu_notify(CPU_DYING... } Before the cpu_notifier is called with CPU_DYING, all interrupts on the dying cpu must be disabled. This guarantees that before tick_notify is called with the CPU_DYING event and sets the clock device pointer to NULL, there can not be any more clock interrupts. When this wasn't done, an unfortunately-timed timer interrupt sometimes caused hangs immediately prior to system suspend: Debug PM is not enabled. To enable partial suspend, rebuild kernel with CONFIG_PM_DEBUG Pass 1 out of 1,PM: Syncing filesystems ... mode=none, tp1=done. 1, flags=5, cycle_tp=, sleep= Freezing user space processes ... (elapsed 0.01 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done. PM: suspend of devices complete after 54.199 msecs PM: late suspend of devices complete after 0.172 msecs Disabling non-boot CPUs ... SMP: CPU1 is offline INFO: rcu_sched detected stalls on CPUs/tasks: { 3} (detected by 0, t=62537 jiffies) Call Trace: [<804baa78>] dump_stack+0x8/0x34 [<8008a2d8>] __rcu_pending+0x4b8/0x55c [<8008adf4>] rcu_check_callbacks+0x78/0x180 [<80037830>] update_process_times+0x40/0x6c [<80072fe4>] tick_sched_timer+0x74/0xe4 [<80050180>] __run_hrtimer.clone.30+0x64/0x140 [<80051150>] hrtimer_interrupt+0x19c/0x4bc [<8000cdb8>] c0_compare_interrupt+0x50/0x88 [<80081b18>] handle_irq_event_percpu+0x5c/0x2f4 [<80086490>] handle_percpu_irq+0x8c/0xc0 [<800811b4>] generic_handle_irq+0x34/0x54 [<800067dc>] do_IRQ+0x18/0x2c [<8000375c>] plat_irq_dispatch+0xd0/0x128 [<80004a04>] ret_from_irq+0x0/0x4 [<80004c40>] r4k_wait+0x20/0x40 [<80006b6c>] cpu_idle+0x98/0xf0 [<805d3988>] start_kernel+0x424/0x440 Signed-off-by: Jon Fraser <jfraser@broadcom.com> Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8160/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Allow BMIPS3300 to utilize SMP ebase relocation codeJon Fraser2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | BMIPS3300 processors do not have the hardware to support SMP, but with a small tweak, the SMP ebase relocation code allows BMIPS3300-based platforms to reuse the S2/S3 power management code from BMIPS4380-based chips. Normally this is as simple as adding one line to prom_init(): board_ebase_setup = &bmips_ebase_setup; Signed-off-by: Jon Fraser <jfraser@broadcom.com> Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8159/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Introduce helper function to change the reset vectorKevin Cernekee2014-11-241-7/+58
| | | | | | | | | | | | | | | | This will need to be called from a few different places, and the logic is starting to get a bit hairy (with the need for IPIs, CPU bug workarounds, and hazards). Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8158/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BMIPS: Align secondary boot sequence with latest firmware releasesKevin Cernekee2014-11-241-11/+1
| | | | | | | | | | | | | | | | | | On some older BMIPS5200 (dual core / quad thread) platforms, the PROM code set up CPU2/CPU3 so they would be started through an NMI instead of through the ACTION register. But this was incompatible with some power management features that were later added, so the scheme was changed so that Linux is fully responsible for booting CPU2/CPU3. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8157/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* clk: ls1x: Update relationship among all clocksKelvin Cheung2014-11-241-29/+80
| | | | | | | | | | | | | | | | | - Add clock lookups for APB devices. - Update clock relationship to make it more exact and clear. _____ _______________________| | OSC ___/ | MUX |___ XXX CLK \___ PLL ___ XXX DIV ___| | |_____| Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-kernel@vger.kernel.org Cc: mturquette@linaro.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8026/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson1B: Add a clockevent/clocksource using PWM TimerKelvin Cheung2014-11-244-31/+266
| | | | | | | | | | This patch add a clockevent/clocksource using PWM Timer for Loongson1B, which is based on earlier work by Tang, Haifeng. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8025/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson1B: Some fixes/updates for LS1BKelvin Cheung2014-11-249-31/+283
| | | | | | | | | | | | | | | | - Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data. (It seems that the MAC controller of LS1B v2.0 can only accept pbl=1) - Add GMAC1 support and setup MUX in terms of PHY mode. - Add CPUFreq support. - Add MUX Register Definitions. - Add PWM Register Definitions. - Update clock register bitfields according to the latest spec. - Update clock related stuff. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8024/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson1B: Improve early printkKelvin Cheung2014-11-242-17/+14
| | | | | | | | | | - Determine serial port for early printk according to kernel command line. - Move to 8250/16550 serial early printk driver. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8023/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Loongson1B: Fix reboot problem on LS1BKelvin Cheung2014-11-242-13/+18
| | | | | | | | | | - Correct the header file of watchdog registers - Use ioremap_nocache() to access watchdog registers instead Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8022/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: DMA: Explain the lack of special handling for R14000/R16000.Ralf Baechle2014-11-241-0/+5
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Clean up nvram headerRafał Miłecki2014-11-243-39/+33
| | | | | | | | | | | | | | 1) Move private defines to the .c file 2) Move SPROM helper to the sprom.c 3) Drop unused code 4) Rename magic to the NVRAM_MAGIC 5) Add const to the char pointer we never modify Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8289/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: BCM47XX: Use mtd as an alternative way/API to get NVRAM contentRafał Miłecki2014-11-241-4/+38
| | | | | | | | | | | | NVRAM can be read using magic memory offset, but after all it's just a flash partition. On platforms where NVRAM isn't needed early we can get it using mtd subsystem. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8266/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Kconfig option to better exercise/debug hybrid FPRsPaul Burton2014-11-242-0/+31
| | | | | | | | | | | | | | | | | | | The hybrid FPR scheme exists to allow for compatibility between existing FP32 code and newly compiled FP64A code. Such code should hopefully be rare in the real world, and for the moment is difficult to come across. All code except that built for the FP64 ABI can correctly execute using the hybrid FPR scheme, so debugging the hybrid FPR implementation can be eased by forcing all such code to use it. This is undesirable in general due to the trap & emulate overhead of the hybrid FPR implementation, but is a very useful option to have for debugging. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7680/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ELF: Set FP mode according to .MIPS.abiflagsPaul Burton2014-11-244-20/+211
| | | | | | | | | | | | | | | This patch reads the .MIPS.abiflags section when it is present, and sets the FP mode of the task accordingly. Any loaded ELF files which do not contain a .MIPS.abiflags section will continue to observe the previous behaviour, that is FR=1 if EF_MIPS_FP64 is set else FR=0. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7681/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ELF: Add definition for the .MIPS.abiflags sectionPaul Burton2014-11-241-0/+25
| | | | | | | | | | | | | | | | | | New toolchains will generate a .MIPS.abiflags section, referenced by a new PT_MIPS_ABIFLAGS program header. This section will provide information about the requirements of the ELF, including the ISA level the code is built for, the ASEs it requires, the size of various registers and its expectations of the floating point mode. This patch introduces a definition of the structure of this section and the program header, for use in a subsequent patch. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7682/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support for hybrid FPRsPaul Burton2014-11-245-10/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Ensure Config5.UFE is clear on bootPaul Burton2014-11-241-1/+1
| | | | | | | | | | | | | As is done for UFR, ensure that userland cannot directly manipulate the mode by clearing the UFE bit during boot. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7677/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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