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* Merge tag 'topic/adl-s-enabling-2021-02-01-1' of ↵Jani Nikula2021-02-0225-129/+417
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm/drm-intel into drm-intel-next Driver Changes: - Add basic support for Alder Lake S, to be shared between drm-intel-next and drm-intel-gt-next Signed-off-by: Jani Nikula <jani.nikula@intel.com> # Conflicts: # drivers/gpu/drm/i915/i915_drv.h From: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210202025620.2212559-1-lucas.demarchi@intel.com
| * drm/i915/adl_s: Add GT and CTX WAs for ADL-SAditya Swarup2021-02-011-13/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Extend Wa_1606931601 and Wa_1409804808 to ADL-S. - Extend Wa_14010919138 and Wa_14010229206 to ADL-S (Madhumitha) - Extend Wa_22010271021 to ADLS (cyokoyam) v2: - Extend Wa_1409804808 and remove unnecessary branching/redundant adls workaround placeholder functions. - Split WAs properly based on previous platforms and applicable ADLS WA. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-9-aditya.swarup@intel.com
| * drm/i915/adl_s: Add display WAs for ADL-SAditya Swarup2021-02-013-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Extend permanent driver WA Wa_1409767108, Wa_14010685332 and Wa_14011294188 to adl-s. - Extend permanent driver WA Wa_1606054188 to adl-s. - Add Wa_14011765242 for adl-s A0 stepping. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-8-aditya.swarup@intel.com
| * drm/i915/adl_s: Update memory bandwidth parametersTejas Upadhyay2021-02-011-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just like RKL, the ADL_S platform also has different memory characteristics from past platforms. Update the values used by our memory bandwidth calculations accordingly. v2: Fix minor nitpick for shifting ADLS case above RKL(based on platform order).(mdroper) Bspec: 64631 Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-7-aditya.swarup@intel.com
| * drm/i915/adl_s: Load DMCAnusha Srivatsa2021-02-011-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Load DMC on ADL_S v2.01. This is the first offcial release of DMC for ADL_S. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-6-aditya.swarup@intel.com
| * drm/i915/display: Add HAS_D12_PLANE_MINIMIZATIONJosé Roberto de Souza2021-02-014-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - As RKL and ADL-S only have 5 planes, primary and 4 sprites and the cursor plane, let's group the handling together under HAS_D12_PLANE_MINIMIZATION. - Also use macro to select pipe irq fault error mask. BSpec: 49251 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-5-aditya.swarup@intel.com
| * drm/i915/adl_s: Re-use TGL GuC/HuC firmwareMatt Roper2021-02-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ADL-S, like RKL, uses the same internal device ID for the GuC and HuC as TGL did, making them all firmware-compatible. Let's re-use TGL's firmware for ADL-S. Bspec: 50668 Cc: John Harrison <John.C.Harrison@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-4-aditya.swarup@intel.com
| * drm/i915/adl_s: Add power wellsLucas De Marchi2021-02-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TGL power wells can be re-used for ADL-S with the exception of the fake power well for TC_COLD, just like DG-1. BSpec: 53597 Bspec: 49231 Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-3-aditya.swarup@intel.com
| * drm/i915/adl_s: Update PHY_MISC programmingMatt Roper2021-02-011-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C is no longer a master, but PHY-D is now. Bspec: 49291 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Aditya Swarup <aditya.swarup@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210129182945.217078-2-aditya.swarup@intel.com
| * drm/i915/adl_s: Update combo PHY master/slave relationshipsMatt Roper2021-01-261-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ADL-S switches up which PHYs are considered a master to other PHYs; PHY-C is no longer a master, but PHY-D is now. Bspec: 49291 Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-11-aditya.swarup@intel.com
| * drm/i915/adl_s: Add vbt port and aux channel settings for adlsAditya Swarup2021-01-261-11/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - ADL-S driver internal mapping uses PORT D, E, F, G for Combo phy B, C, D and E. - Add ADLS specific port mappings for vbt port dvo settings. - Select appropriate AUX CH specific to ADLS based on port mapping. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-10-aditya.swarup@intel.com
| * drm/i915/adl_s: Add adl-s ddc pin mappingAditya Swarup2021-01-263-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ADL-S requires TC pins to set up ddc for Combo PHY B, C, D and E. Combo PHY A still uses the old ddc pin mapping. From VBT, ddc pin info suggests the following mapping: VBT DRIVER DDI B->ddc_pin=2 should translate to PORT_D->0x9 DDI C->ddc_pin=3 should translate to PORT_E->0xa DDI D->ddc_pin=4 should translate to PORT_F->0xb DDI E->ddc_pin=5 should translate to PORT_G->0xc Adding pin map to facilitate this translation as we cannot use existing icl ddc pin map due to conflict with DDI B and DDI C info. Bspec:20124 v2: Replace IS_ALDERLAKE_S() with HAS_PCH_ADP() as the pin map pairing depends on the PCH being used rather than the platform.(mdroper) v3: - Modify adls_port_to_ddc_pin() to make PHY_A the special case for check, else return pin mapping based on correct arithmetic with phy offset. Remove redundant platform checks and use HAS_PCH_ADP() instead of IS_ALDERLAKE_S() in intel_hdmi_ddc_pin().(mdroper) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-9-aditya.swarup@intel.com
| * drm/i915/adl_s: Initialize display for ADL-SAditya Swarup2021-01-261-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialize display outputs for ADL-S. ADL-S has 5 display outputs -> 1 eDP, 2 HDMI and 2 DP++ outputs. v2: - Use PORT_TCx instead of PORT_D,E.. to stay consistent with other platforms.(mdroper) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-8-aditya.swarup@intel.com
| * drm/i915/adl_s: Configure Port clock registers for ADL-SAditya Swarup2021-01-263-24/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add changes to configure port clock registers for ADL-S. Combo phy port clocks are configured by DPCLKA_CFGCR0 and DPCLKA_CFGCR1 registers. The DDI to internal clock mappings in DPCLKA_CFGCR0 register for ADL-S translates to DDI A -> DDIA DDI B -> USBC1 DDI I -> USBC2 For DPCLKA_CFGCR1 DDI J -> USBC3 DDI K -> USBC4 Bspec: 50287 Bspec: 53812 Bspec: 53723 v2: Replace I915_READ() with intel_de_read().(Jani) v3: - Use reg variable to assign ADLS specific registers inorder to replace branching with intel_de_read/write() calls.(mdroper) - Reuse icl_get_ddi_pll() for ADLS to fix issue with updating active dpll on driver load.(aswarup) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-7-aditya.swarup@intel.com
| * drm/i915/adl_s: Configure DPLL for ADL-SAditya Swarup2021-01-262-6/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add changes for configuring DPLL for ADL-S - Reusing DG1 DPLL 2 & DPLL 3 for ADL-S - Extend CNL macro to choose DPLL_ENABLE for ADL-S. - Select CFGCR0 and CFGCR1 for ADL-S plls. On BSpec: 53720 PLL arrangement dig for adls: DPLL2 cfgcr is programmed using _ADLS_DPLL3_CFGCR(0/1) DPLL3 cfgcr is programmed using _ADLS_DPLL4_CFGCR(0/1) v2 (Lucas): add missing update_ref_clks Bspec: 50288 Bspec: 50289 Bspec: 49443 v3 : Adding another bit to HDPORT_DPLL_USED_MASK bitfield for DPLL3_USED.(mdroper) Bspec: 53707 v4: BSpec 53723 has been updated with note - DPLL2 is controlled by DPLL4 CFGCR 0/1.(mdroper) Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-6-aditya.swarup@intel.com
| * drm/i915/adl_s: Add PHYs for Alderlake SAnusha Srivatsa2021-01-262-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alderlake-S has 5 combo phys, add reg definitions for combo phys and update the port to phy helper for ADL-S. v2: - Change IS_GEN() >= 12 to IS_TIGERLAKE() in intel_phy_is_tc() and return false for platforms RKL,DG1 and ADLS.(mdroper) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-5-aditya.swarup@intel.com
| * drm/i915/adl_s: Add Interrupt SupportAnusha Srivatsa2021-01-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ADLS follows ICP/TGP like interrupts. v2: Use "INTEL_PCH_TYPE(dev_priv) >= PCH_ICP" of hpd_icp (Lucas) Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-4-aditya.swarup@intel.com
| * drm/i915/adl_s: Add PCH supportAnusha Srivatsa2021-01-262-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Alderpoint(ADP) PCH used with Alderlake-S. v2: - Use drm_dbg_kms and drm_WARN_ON based on Jani's feedback.(aswarup) Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Caz Yokoyama <caz.yokoyama@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125140753.347998-3-aditya.swarup@intel.com
| * x86/gpu: Add Alderlake-S stolen memory supportCaz Yokoyama2021-01-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alderlake-S is a Gen 12 based hybrid processor architecture. As it belongs to Gen 12 family, it uses the same GTT stolen memory settings like its predecessors - ICL(Gen 11) and TGL(Gen 12). Inherit gen11 and gen 9 quirks for determining base and size of stolen memory. Bspec: 52055 Bspec: 49589 Bspec: 49636 Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: x86@kernel.org Cc: Ingo Molnar <mingo@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Borislav Petkov <bp@suse.de> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Acked-by: Borislav Petkov <bp@suse.de> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210126001744.29442-2-aditya.swarup@intel.com
| * drm/i915/adl_s: Add ADL-S platform info and PCI idsCaz Yokoyama2021-01-206-1/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add the initial platform information for Alderlake-S. - Specify ppgtt_size value - Add dma_mask_size - Add ADLS REVIDs - HW tracking(Selective Update Tracking Enable) has been removed from ADLS. Disable PSR2 till we enable software/ manual tracking. v2: - Add support for different ADLS SOC steppings to select correct GT/DISP stepping based on Bspec 53655 based on feedback from Matt Roper.(aswarup) v3: - Make display/gt steppings info generic for reuse with TGL and ADLS. - Modify the macros to reuse tgl_revids_get() - Add HTI support to adls device info.(mdroper) v4: - Rebase on TGL patch for applying WAs based on stepping info from Matt Roper's feedback.(aswarup) v5: - Replace macros with PCI IDs in revid to stepping table. v6: remove stray adls_revids (Lucas) Bspec: 53597 Bspec: 53648 Bspec: 53655 Bspec: 48028 Bspec: 53650 BSpec: 50422 Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210119192931.1116500-2-lucas.demarchi@intel.com
| * drm/i915/tgl: Use TGL stepping info for applying WAsAditya Swarup2021-01-206-43/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TGL adds another level of indirection for applying WA based on stepping information rather than PCI REVID. So change TGL_REVID enum into stepping enum and use PCI REVID as index into revid to stepping table to fetch correct display and GT stepping for application of WAs as suggested by Matt Roper. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210119192931.1116500-1-lucas.demarchi@intel.com
* | drm/i915/bios: tidy up child device debug loggingJani Nikula2021-02-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the child device details easier to read by turning this: [drm:parse_ddi_port [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:1 DP:0 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [drm:parse_ddi_port [i915]] VBT HDMI level shift for port B: 8 [drm:parse_ddi_port [i915]] VBT DP max link rate for port B: 810000 [drm:parse_ddi_port [i915]] Port C VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [drm:parse_ddi_port [i915]] VBT HDMI level shift for port C: 8 [drm:parse_ddi_port [i915]] VBT (e)DP boost level for port C: 3 [drm:parse_ddi_port [i915]] VBT HDMI boost level for port C: 1 [drm:parse_ddi_port [i915]] VBT DP max link rate for port C: 810000 into this: [drm:parse_ddi_port [i915]] Port B VBT info: CRT:0 DVI:1 HDMI:1 DP:0 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [drm:parse_ddi_port [i915]] Port B VBT HDMI level shift: 8 [drm:parse_ddi_port [i915]] Port B VBT DP max link rate: 810000 [drm:parse_ddi_port [i915]] Port C VBT info: CRT:0 DVI:1 HDMI:1 DP:1 eDP:0 LSPCON:0 USB-Type-C:0 TBT:0 DSC:0 [drm:parse_ddi_port [i915]] Port C VBT HDMI level shift: 8 [drm:parse_ddi_port [i915]] Port C VBT (e)DP boost level: 3 [drm:parse_ddi_port [i915]] Port C VBT HDMI boost level: 1 [drm:parse_ddi_port [i915]] Port C VBT DP max link rate: 810000 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210127084534.24406-1-jani.nikula@intel.com
* | drm/i915/hdcp: disable the QSES check for HDCP2.2 over MSTJuston Li2021-02-011-30/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Like the patch to disable QSES for HDCP 1.4 over MST https://patchwork.freedesktop.org/patch/415297/ the HDCP2.2 spec doesn't require QSES as well and we've seen QSES not supported on a couple HDCP2.2 docks so far (Dell WD19 and Lenovo LDC-G2) Remove it for now until we get a better idea of how widely supported QSES is and how to support it optionally. Signed-off-by: Juston Li <juston.li@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210127065034.2501119-4-juston.li@intel.com
* | drm/i915: Don't check tc_mode unless dealing with a TC PHYVille Syrjälä2021-01-301-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | We shouldn't really trust tc_mode on non-TC PHYs since we never initialize it explicitly. So let's check for the PHY type first. Fortunately TC_PORT_TBT_ALT happens to be zero so I don't think there's an actual bug here, just a possibility for a future one if someone rearranges the enum values. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128155948.13678-5-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
* | drm/i915: Move HDMI vswing programming to the right placeVille Syrjälä2021-01-301-15/+15
| | | | | | | | | | | | | | | | | | | | The documented programming sequence indicates the correct point for the vswing programming is just before we enable the DDI. Make it so. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128155948.13678-4-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
* | drm/i915: Power up combo PHY lanes for for HDMI as wellVille Syrjälä2021-01-301-0/+2
| | | | | | | | | | | | | | | | | | | | Currently we only explicitly power up the combo PHY lanes for DP. The spec says we should do it for HDMI as well. Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128155948.13678-3-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
* | drm/i915: Extract intel_ddi_power_up_lanes()Ville Syrjälä2021-01-301-16/+19
| | | | | | | | | | | | | | | | | | | | Reduce the copypasta by pulling the combo PHY lane power up stuff into a helper. We'll have a third user soon. Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128155948.13678-2-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
* | drm/i915: Skip vswing programming for TBTVille Syrjälä2021-01-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In thunderbolt mode the PHY is owned by the thunderbolt controller. We are not supposed to touch it. So skip the vswing programming as well (we already skipped the other steps not applicable to TBT). Touching this stuff could supposedly interfere with the PHY programming done by the thunderbolt controller. Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128155948.13678-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
* | drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detectedImre Deak2021-01-291-21/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Atm, the driver programs explicitly the default transparent link training mode (0x55) to DP_PHY_REPEATER_MODE even if no LTTPRs are detected. This conforms to the spec (3.6.6.1): "DP upstream devices that do not enable the Non-transparent mode of LTTPRs shall program the PHY_REPEATER_MODE register (DPCD Address F0003h) to 55h (default) prior to link training" however writing the default value to this DPCD register seems to cause occasional link training errors at least for a DELL WD19TB TBT dock, when no LTTPRs are detected. Writing to DP_PHY_REPEATER_MODE will also cause an unnecessary timeout on systems without any LTTPR. To fix the above two issues let's assume that setting the default mode is redundant when no LTTPRs are detected. Keep the existing behavior and program the default mode if more than 8 LTTPRs are detected or in case the read from DP_PHY_REPEATER_CNT returns an invalid value. References: https://gitlab.freedesktop.org/drm/intel/-/issues/2801 Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Khaled Almahallawy <khaled.almahallawy@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210118183143.1145707-1-imre.deak@intel.com
* | drm/i915: Implement async flips for vlv/chvVille Syrjälä2021-01-294-6/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for async flips on vlv/chv. Unlike all the other platforms vlv/chv do not use the async flip bit in DSPCNTR and instead we select between async vs. sync flips based on the surface address register. The normal DSPSURF generates sync flips DSPADDR_VLV generates async flips. And as usual the interrupt bits are different from the other platforms. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-12-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
* | drm/i915: Implement async flip for ilk/snbVille Syrjälä2021-01-293-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | Add support for async flips on ivb/hsw. Again no need for any workarounds and just have to deal with the interrupt bits being shuffled around a bit. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-11-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
* | drm/i915: Implement async flip for ivb/hswVille Syrjälä2021-01-293-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for async flips on ivb/hsw. Unlike bdw+ we don't need any workarounds to disable async flips. Apart from that the only real difference from the bdw implementation is the location of the flip_done interrupt bits. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-10-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
* | drm/i915: Implement async flips for bdwVille Syrjälä2021-01-294-14/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement async flip support for BDW. The implementation is similar to the skl+ code. And just like skl/bxt/glk bdw also needs the disable w/a, thus we need to plumb the desired state of the async flip all the way down to i9xx_plane_ctl_crtc(). According to the spec we do need to bump the surface alignment to 256KiB for this. Async flips require an X-tiled buffer so we don't have to worry about linear. Cc: Karthik B S <karthik.b.s@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-9-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
* | drm/i915: Limit plane stride to below TILEOFF.x limitVille Syrjälä2021-01-293-16/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Limit pre-skl plane stride to below 4k or 8k pixels (depending on the platform). We do this in order guarantee that TILEOFF/OFFSET.x does not get too big. Currently this is not a problem as we align SURF to 4k, and so TILEOFF/OFFSET only have to deal with a single tile's worth of pixels. But for async flips we're going to have to bump SURF alignment to 256k, and thus we can no longer guarantee TILEOFF/OFFSET.x will stay within acceptable bounds. We can avoid this by borrowing a trick from the skl+ code and limit the max plane stride to whatever value we can fit into TILEOFF/OFFSET.x. The slight downside is that we may end up doing GTT remapping in a few more cases where previously we did not have to. But since that will only happen with huge buffers I'm not really concerned about it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-3-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
* | drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_neededJosé Roberto de Souza2021-01-293-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | As it now it is always required for GEN12+ the is_16gb_dimm name do not make sense for GEN12+. v2: - Updated comment on top of "dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);" Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-3-jose.souza@intel.com
* | drm/i915/gen11+: Only load DRAM information from pcodeJosé Roberto de Souza2021-01-294-75/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up to now we were reading some DRAM information from MCHBAR register and from pcode what is already not good but some GEN12(TGL-H and ADL-S) platforms have MCHBAR DRAM information in different offsets. This was notified to HW team that decided that the best alternative is always apply the 16gb_dimm watermark adjustment for GEN12+ platforms and read the remaning DRAM information needed to other display programming from pcode. So here moving the DRAM pcode function to intel_dram.c, removing the duplicated fields from intel_qgv_info, setting and using information from dram_info. v2: - bring back num_points to intel_qgv_info as num_qgv_point can be overwritten in icl_get_qgv_points() - add gen12_get_dram_info() and simplify gen11_get_dram_info() Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-2-jose.souza@intel.com
* | drm/i915: Nuke not needed members of dram_infoJosé Roberto de Souza2021-01-293-42/+12
| | | | | | | | | | | | | | | | | | Valid, ranks and bandwidth_kbps are set into dram_info but are not used anywhere else so nuking it. Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-1-jose.souza@intel.com
* | drm/i915: Fix the MST PBN divider calculationImre Deak2021-01-281-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Atm the driver will calculate a wrong MST timeslots/MTP (aka time unit) value for MST streams if the link parameters (link rate or lane count) are limited in a way independent of the sink capabilities (reported by DPCD). One example of such a limitation is when a MUX between the sink and source connects only a limited number of lanes to the display and connects the rest of the lanes to other peripherals (USB). Another issue is that atm MST core calculates the divider based on the backwards compatible DPCD (at address 0x0000) vs. the extended capability info (at address 0x2200). This can result in leaving some part of the MST BW unused (For instance in case of the WD19TB dock). Fix the above two issues by calculating the PBN divider value based on the rate and lane count link parameters that the driver uses for all other computation. Bugzilla: https://gitlab.freedesktop.org/drm/intel/-/issues/2977 Cc: Lyude Paul <lyude@redhat.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: <stable@vger.kernel.org> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjala <ville.syrjala@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125173636.1733812-2-imre.deak@intel.com
* | drm/dp/mst: Export drm_dp_get_vc_payload_bw()Imre Deak2021-01-282-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will be needed by the next patch where the driver calculates the BW based on driver specific parameters, so export it. At the same time sanitize the function params, passing the more natural link rate instead of the encoding of the same rate. v2: - Fix function documentation. (Lyude) Cc: Lyude Paul <lyude@redhat.com> Cc: Ville Syrjala <ville.syrjala@intel.com> Cc: <stable@vger.kernel.org> Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210125173636.1733812-1-imre.deak@intel.com
* | drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MSTSean Paul2021-01-281-11/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HDCP 1.4 spec does not require the QUERY_STREAM_ENCRYPTION_STATUS check, it was always a nice-to-have. After deploying this across various devices, we've determined that some MST bridge chips do not properly support this call for HDCP 1.4 (namely Synaptics and Realtek). I had considered creating a quirk for this, but I think it's more prudent to just disable the check entirely since I don't have an idea how widespread support is. Changes in v2: -Rebased on -tip Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210106223909.34476-1-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20210121172620.33066-1-sean@poorly.run
* | drm/i915/display: Prevent double YUV range correction on HDR planesAndres Calderon Jaramillo2021-01-282-55/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prevent the ICL HDR plane pipeline from performing YUV color range correction twice when the input is in limited range. This is done by removing the limited-range code from icl_program_input_csc(). Before this patch the following could happen: user space gives us a YUV buffer in limited range; per the pipeline in [1], the plane would first go through a "YUV Range correct" stage that expands the range; the plane would then go through the "Input CSC" stage which would also expand the range because icl_program_input_csc() would use a matrix and an offset that assume limited-range input; this would ultimately cause dark and light colors to appear darker and lighter than they should respectively. This is an issue because if a buffer switches between being scanned out and being composited with the GPU, the user will see a color difference. If this switching happens quickly and frequently, the user will perceive this as a flickering. [1] https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-icllp-vol12-displayengine_0.pdf#page=281 Cc: stable@vger.kernel.org Signed-off-by: Andres Calderon Jaramillo <andrescj@chromium.org> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201215224219.3896256-1-andrescj@google.com
* | drm/i915: WARN if plane src coords are too bigVille Syrjälä2021-01-272-0/+11
| | | | | | | | | | | | | | | | | | Inform us if we're buggy and are about to exceed the size of the bitfields in the plane TILEOFF/OFFSET registers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111163711.12913-2-ville.syrjala@linux.intel.com Reviewed-by: Karthik B S <karthik.b.s@intel.com>
* | drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoderManasi Navare2021-01-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | DSI transcoder does not support VRR and hence skip the HW state readout if its a DSI transcoder. Fixes: c7f0f4372b30 ("drm/i915/display: Add HW state readout for VRR") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210126185224.32340-1-manasi.d.navare@intel.com
* | drm/i915: Do a bit more initial readout for dbufVille Syrjälä2021-01-262-6/+48
| | | | | | | | | | | | | | | | | | | | | | Readout the dbuf related stuff during driver init/resume and stick it into our dbuf state. v2: Keep crtc_state->wm.skl.ddb Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-9-ville.syrjala@linux.intel.com
* | drm/i915: Encapsulate dbuf state handling harderVille Syrjälä2021-01-265-271/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make the dbuf state computation less fragile let's make it stand on its own feet by not requiring someone to peek into a crystall ball ahead of time to figure out which pipes need to be added to the state under which potential future conditions. Instead we compute each piece of the state as we go along, and if any fallout occurs that affects more than the current set of pipes we add the affected pipes to the state naturally. That requires that we track a few extra thigns in the global dbuf state: dbuf slices for each pipe, and the weight each pipe has when distributing the same set of slice(s) between multiple pipes. Easy enough. We do need to follow a somewhat careful sequence of computations though as there are several steps involved in cooking up the dbuf state. Thoguh we could avoid some of that by computing more things on demand instead of relying on earlier step of the algorithm to have filled it out. I think the end result is still reasonable as the entire sequence is pretty much consolidated into a single function instead of being spread around all over. The rough sequence is this: 1. calculate active_pipes 2. calculate dbuf slices for every pipe 3. calculate total enabled slices 4. calculate new dbuf weights for any crtc in the state 5. calculate new ddb entry for every pipe based on the sets of slices and weights, and add any affected crtc to the state 6. calculate new plane ddb entries for all crtcs in the state, and add any affected plane to the state so that we'll perform the requisite hw reprogramming And as a nice bonus we get to throw dev_priv->wm.distrust_bios_wm out the window. v2: Keep crtc_state->wm.skl.ddb Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-8-ville.syrjala@linux.intel.com
* | drm/i915: Extract intel_crtc_dbuf_weights()Ville Syrjälä2021-01-261-55/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | Extract the code to calculate the weights used to chunk up the dbuf between pipes. There's still extra stuff in there that shouldn't be there and must be moved out, but that requires a bit more state to be tracked in the dbuf state. v2: Keep crtc_state->wm.skl.ddb Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-7-ville.syrjala@linux.intel.com
* | drm/i915: Add pipe ddb entries into the dbuf stateVille Syrjälä2021-01-262-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dbuf state will be where we collect all the inter-pipe dbuf allocation stuff. Start by adding the actual per-pipe ddb entries there. Originally the plan was to move them there outright, but that no longer works as we're no longer guaranteed to have a dbuf state when it comes time to sanity check the ddb overlaps in skl_commit_modeset_enables(). I think when I wrote this originally we did the watermark/ddb calculation last, and so we couldn't have any crtcs in the state w/o also having the dbuf state. But that has since changed and we do the watermark/ddb calculation much earlier, and thus it is now possible to commit crtcs w/o a dbuf state. So we keep another copy of the information in the crtc state. v2: Rebase v3: Duplicate the entries instead of moving Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-6-ville.syrjala@linux.intel.com
* | drm/i915: Introduce skl_ddb_entry_for_slices()Ville Syrjälä2021-01-261-37/+18
| | | | | | | | | | | | | | | | | | | | | | Generalize icl_get_first_dbuf_slice_offset() into something that just gives us the start+end of the dbuf chunk covered by the specified slices as a standard ddb entry. Initial idea was to use it during readout as well, but we shall see. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-5-ville.syrjala@linux.intel.com
* | drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä2021-01-262-16/+21
| | | | | | | | | | | | | | | | | | Put the code into a function with a descriptive name. Also relocate the code a bit help future work. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-4-ville.syrjala@linux.intel.com
* | drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä2021-01-261-12/+10
| | | | | | | | | | | | | | | | | | skl_compute_dbuf_slices() has no use for the crtc state, so just pass the crtc itself. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210122205633.18492-3-ville.syrjala@linux.intel.com
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-29 14:11:32 +0000