summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* phy: qcom-qmp-combo: remove QPHY_PCS_LFPS_RXTERM_IRQ_STATUS regDmitry Baryshkov2023-01-181-5/+0
| | | | | | | | | The QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113212102.421491-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qualcomm: qmp-ufs: rename qmp_ufs_offsets_v5 to qmp_ufs_offsetsDmitry Baryshkov2023-01-181-3/+3
| | | | | | | | | | All currently known QMP UFS PHYs have the same offsets for register sub-regions. Instead of using qmp_ufs_offsets_v5 for older generations of PHYs, rename the offsets struct instance to remove _v5 suffix. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230113195515.407866-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ti: j721e-wiz: Add support to enable LN23 Type-C swapSinthu Raja2023-01-181-5/+33
| | | | | | | | | | | | | | | | The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the USB PHY that is integrated into the SerDes IP. The WIZ control register has to be configured to support this lane swap feature. The support for swapping lanes 2 and 3 is missing and therefore add support to configure the control register to swap between lanes 2 and 3 if PHY type is USB. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230113150615.19375-3-sinthu.raja@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specifiedSinthu Raja2023-01-181-10/+28
| | | | | | | | | | | | | | | It's possible that the Type-C plug orientation on the DIR line will be implemented through hardware design. In that situation, there won't be an external GPIO line available, but the driver still needs to address this since the DT won't use the typec-dir-gpios property. Add code to handle LN10 Type-C swap if typec-dir-gpios property is not specified in DT. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230113150615.19375-2-sinthu.raja@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Add HS G4 mode support to SC8280XP SoCManivannan Sadhasivam2023-01-171-0/+8
| | | | | | | | | | | | UFS PHY in SC8280XP SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-13-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Add HS G4 mode support to SM8450 SoCManivannan Sadhasivam2023-01-171-0/+8
| | | | | | | | | | | | UFS PHY in SM8450 SoC is capable of operating at HS G4 mode and the init sequence is compatible with SM8350. Hence, add the tbls_hs_g4 instance reusing the G4 init sequence of SM8350. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-12-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Add HS G4 mode support to SM8350 SoCManivannan Sadhasivam2023-01-171-0/+36
| | | | | | | | | | | UFS PHY in SM8350 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-11-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Avoid setting HS G3 specific registersManivannan Sadhasivam2023-01-171-7/+0
| | | | | | | | | | | | | | | | | | | | | SM8350 default init sequence sets some PCS registers to HS G3, thereby disabling HS G4 mode. This has the effect on MPHY capability negotiation between the host and the device during link startup and causes the PA_MAXHSGEAR to G3 irrespective of device max gear. Due to that, the agreed gear speed determined by the UFS core will become G3 only and the platform won't run at G4. So, let's remove setting these registers for SM8350 as like other G4 compatible platforms. One downside of this is that, when the board design uses non-G4 compatible device, then MPHY will continue to run in the default mode (G4) even if UFSHCD runs in G3. But this is the case for other platforms as well. Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-10-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Add HS G4 mode support to SM8250 SoCManivannan Sadhasivam2023-01-172-1/+62
| | | | | | | | | | | | UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-9-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Add HS G4 mode support to SM8150 SoCManivannan Sadhasivam2023-01-171-0/+36
| | | | | | | | | | | UFS PHY in SM8150 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-8-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Move HS Rate B register setting to tbls_hs_bManivannan Sadhasivam2023-01-171-5/+32
| | | | | | | | | | | | | | Since now there is support for configuring the HS Rate B mode properly, let's move the register setting to tbls_hs_b struct for all SoCs. This allows the PHY to be configured in Rate A initially and then in Rate B if requested by the UFS driver. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-7-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Add support for configuring PHY in HS G4 modeManivannan Sadhasivam2023-01-171-0/+9
| | | | | | | | | | | | | Add separate tables_hs_g4 instance to allow the PHY driver to configure the PHY in HS G4 mode. The individual SoC configs need to supply the Rx, Tx and PCS register setting in tables_hs_g4 and the UFS driver can request the Hs G4 mode by calling phy_set_mode_ext() with submode set to UFS_HS_G4. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-6-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Add support for configuring PHY in HS Series B modeManivannan Sadhasivam2023-01-171-0/+15
| | | | | | | | | | | | | Add separate tables_hs_b instance to allow the PHY driver to configure the PHY in HS Series B mode. The individual SoC configs need to supply the serdes register setting in tables_hs_b and the UFS driver can request the Series B mode by calling phy_set_mode() with mode set to PHY_MODE_UFS_HS_B. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-5-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Move register settings to qmp_phy_cfg_tbls structManivannan Sadhasivam2023-01-171-83/+113
| | | | | | | | | | | | | As done for Qcom PCIe PHY driver, let's move the register settings to the common qmp_phy_cfg_tbls struct. This helps in adding any additional PHY settings needed for functionalities like HS-G4 in the future by adding one more instance of the qmp_phy_cfg_tbls. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-4-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Rename MSM8996 PHY definitionsManivannan Sadhasivam2023-01-171-11/+11
| | | | | | | | | | | | Only MSM8996 is using "_ufs_" naming convention for PHY definitions instead of "_ufsphy_" as like other SoCs. So to maintain the uniformity, let's rename all of the definitions to use "_ufsphy_". Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-3-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitionsManivannan Sadhasivam2023-01-171-73/+73
| | | | | | | | | | | | Following the other QMP PHY drivers like PCIe, let's remove the "_tbl" suffix from the qmp_phy_init_tbl definitions. This helps in maintaining the uniformity across all of the QMP PHY drivers. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-2-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: convert meson-gxl-usb2-phy.txt to dt-schemaNeil Armstrong2023-01-142-21/+56
| | | | | | | | | | Convert the Amlogic Meson GXL USB2 PHY bindings to dt-schema. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20221117-b4-amlogic-bindings-convert-v2-8-36ad050bb625@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp: Add SM6125 UFS PHY supportLux Aliaga2023-01-131-0/+5
| | | | | | | | | | | The SM6125 UFS PHY is compatible with the one from SM6115. Add a compatible for it and modify the config from SM6115 to make them compatible with the SC8280XP binding Signed-off-by: Lux Aliaga <they@mint.lgbt> Reviewed-by: Martin Botka <martin.botka@somainline.org> Link: https://lore.kernel.org/r/20230108195336.388349-4-they@mint.lgbt Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: Add QMP UFS PHY compatible for SM6125Lux Aliaga2023-01-131-0/+1
| | | | | | | | | | | Document the QMP UFS PHY compatible for SM6125. Signed-off-by: Lux Aliaga <they@mint.lgbt> Reviewed-by: Martin Botka <martin.botka@somainline.org> Acked-by: Dhruva Gole <d-gole@ti.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230108195336.388349-3-they@mint.lgbt Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: qcom,sc7180-qmp-usb3-dp-phy: correct clocks per variantsKrzysztof Kozlowski2023-01-131-10/+62
| | | | | | | | | | | | | | | | Different variants of Qualcomm USB3 DP PHY take different clocks (according to upstream DTS and Linux driver): sc7280-herobrine-crd.dtb: phy-wrapper@88e9000: clocks: [[43, 151], [39, 0], [43, 153]] is too short sc7280-herobrine-crd.dtb: phy-wrapper@88e9000: clock-names:1: 'cfg_ahb' was expected ... sm8250-hdk.dtb: phy@88e9000: clocks: [[46, 185], [44, 0], [46, 187]] is too short sm8250-hdk.dtb: phy@88e9000: clock-names:1: 'cfg_ahb' was expected Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221225115944.55425-2-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: qcom,sc7180-qmp-usb3-dp-phy: correct SC7280 compatiblesKrzysztof Kozlowski2023-01-131-6/+11
| | | | | | | | | | | USB3 DP PHY on SC7280 is used with SM8250 fallback: sc7280-herobrine-evoker.dtb: phy-wrapper@88e9000: compatible: ['qcom,sc7280-qmp-usb3-dp-phy', 'qcom,sm8250-qmp-usb3-dp-phy'] is too long Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221225115944.55425-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: qcom,qusb2: do not define properties in "if" blockKrzysztof Kozlowski2023-01-131-75/+85
| | | | | | | | | | | | | | | It is more readable to define properties in top-level "properties:" and restrict them (if needed) per compatible in the "if" block. Defining properties in "if" block does not work correctly with additionalProperties:false: sc7180-trogdor-pazquel-lte-ti.dtb: phy@88e3000: 'qcom,bias-ctrl-value', 'qcom,charge-ctrl-value', 'qcom,hsdisc-trim-value', 'qcom,imp-res-offset-value', 'qcom,preemphasis-level', 'qcom,preemphasis-width' do not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221224154226.43417-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: qcom,usb-snps-femto-v2: use fallback compatiblesKrzysztof Kozlowski2023-01-131-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | Document SoC-specific compatibles with generic fallback (e.g. qcom,usb-snps-hs-7nm-phy) already used in DTSI. Add SoC-specific compatibles for PHY on SDX55 and SDX65. This disallows usage of the qcom,usb-snps-hs-5nm-phy and qcom,usb-snps-hs-7nm-phy generic compatibles alone. Do not touch remaining two compatibles - qcom,usb-snps-femto-v2-phy and qcom,sc8180x-usb-hs-phy - because there are no upstream users, so not sure what was the intention for them. This fixes warnings like: sa8295p-adp.dtb: phy@88e5000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,sc8280xp-usb-hs-phy', 'qcom,usb-snps-hs-5nm-phy'] is too long 'qcom,sc8280xp-usb-hs-phy' is not one of ['qcom,sm8150-usb-hs-phy', 'qcom,sm8250-usb-hs-phy', 'qcom,sm8350-usb-hs-phy', 'qcom,sm8450-usb-hs-phy'] 'qcom,usb-snps-hs-7nm-phy' was expected Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221223161835.112079-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: renesas: r8a779f0-eth-serdes: Remove retry code in .init()Yoshihiro Shimoda2023-01-131-10/+4
| | | | | | | | | | Remove retry code in r8a779f0_eth_serdes_init() because r8a779f0_eth_serdes_chan_setting() was fixed so that no timeout happened in the initializing procedure. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221226065316.3895480-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: renesas: r8a779f0-eth-serdes: Add .power_on() into phy_opsYoshihiro Shimoda2023-01-131-28/+29
| | | | | | | | | | | | | Add r8a779f0_eth_serdes_power_on() to initialize the hardware for each channel from the step 9 or later on the datasheet. In other words, the procedure from the step 1 to 8 is for all channel and it is needed once only. So, the .init() in any channel instance is called, this driver initializes the hardware from step 1 to 8. And then, .power_on() is called, this driver initializes the hardware from step 9 or later. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20221226065316.3895480-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: qcom,usb-hsic-phy: convert to DT schemaKrzysztof Kozlowski2023-01-132-65/+67
| | | | | | | | | Convert Qualcomm USB HSIC PHY bindings to DT schema. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221222155805.139284-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: tegra: xusb: Support USB role default modeHaotien Hsu2023-01-131-0/+17
| | | | | | | | | Support role-switch-default-mode property when usb-role-switch is enabled. Signed-off-by: Haotien Hsu <haotienh@nvidia.com> Link: https://lore.kernel.org/r/20221216042146.99307-1-haotienh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-usb: Add Qualcomm SM6115 / SM4250 USB3 PHY supportBhupesh Sharma2023-01-131-0/+3
| | | | | | | | | | | Enable SM6115 / SM4250 USB3 PHY support by adding the qmp_phy_cfg data. Since this PHY is the same as the one used on QCM2290, reuse the QCM2290 qmp_phy_cfg data already available. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20221213122843.454845-4-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-usb: Fix QSERDES_V3_RX_UCDR_PI_CONTROLS init valBhupesh Sharma2023-01-131-1/+1
| | | | | | | | | | | | As per the Qualcomm QMP v3 PHY programming guide document, QSERDES_V3_RX_UCDR_PI_CONTROLS configuration should be set to an initial configuration value of 0x80. Fix the same. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20221213122843.454845-3-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: qcom,qmp-usb: Add SM6115 / SM4250 USB3 PHYBhupesh Sharma2023-01-131-0/+3
| | | | | | | | | Add dt-bindings for USB3 PHY found on Qualcomm SM6115 / SM4250 SoC. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221213122843.454845-2-bhupesh.sharma@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: mediatek,tphy: add support for mt7986Frank Wunderlich2023-01-121-0/+1
| | | | | | | | | | | | Add compatible string for mt7986. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20230106152845.88717-2-linux@fw-web.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: sun4i-usb: Replace types with explicit quirk flagsAndre Przywara2023-01-121-36/+15
| | | | | | | | | | | | | | | | So far we were assigning some crude "type" (SoC name, really) to each Allwinner USB PHY model, then guarding certain quirks based on this. This does not only look weird, but gets more or more cumbersome to maintain. Remove the bogus type names altogether, instead introduce flags for each quirk, and explicitly check for them. This improves readability, and simplifies future extensions. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230109012223.4079299-4-andre.przywara@arm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: sun4i-usb: add support for the USB PHY on F1C100s SoCIcenowy Zheng2023-01-121-0/+10
| | | | | | | | | | | | The F1C100s SoC has one USB OTG port connected to a MUSB controller. Add support for its USB PHY. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20230109012223.4079299-3-andre.przywara@arm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: add binding document for Allwinner F1C100s USB PHYIcenowy Zheng2023-01-121-0/+83
| | | | | | | | | | | | | | | | | | | | Allwinner F1C100s has the most simple USB PHY among all Allwinner SoCs, because it has only one OTG USB controller, no host-only OHCI/EHCI controllers. Add a binding document for it. Following the current situation of one YAML file per SoC, this one is based on allwinner,sun8i-v3s-usb-phy.yaml, but with OHCI/EHCI-related bits removed. (The same driver in Linux, phy-sun4i-usb, covers all these binding files now.) Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20230109012223.4079299-2-andre.przywara@arm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: tegra: xusb: Add Tegra234 supportSing-Han Chen2023-01-124-3/+91
| | | | | | | | | | | | | | | | | | | Add support for the XUSB pad controller found on Tegra234 SoCs. It is mostly similar to the same IP found on Tegra194, because most of the Tegra234 XUSB PADCTL registers definition and programming sequence are the same as Tegra194, Tegra234 XUSB PADCTL can share the same driver with Tegra186 and Tegra194 XUSB PADCTL. Introduce a new feature, USB2 HW tracking, for Tegra234. The feature is to enable HW periodical PAD tracking which measure and capture the electric parameters of USB2.0 PAD. Signed-off-by: Sing-Han Chen <singhanc@nvidia.com> Co-developed-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230111110450.24617-6-jonathanh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: tegra: xusb: Disable trk clk when not in useWayne Chang2023-01-121-2/+4
| | | | | | | | | | | | | Pad tracking is a one-time calibration for Tegra186 and Tegra194. Clk should be disabled after calibration. Disable clk after calibration. While at it add 100us delay for HW recording the calibration value. Signed-off-by: Wayne Chang <waynec@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Link: https://lore.kernel.org/r/20230111110450.24617-5-jonathanh@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp: move type-specific headers to particular driverDmitry Baryshkov2023-01-125-14/+17
| | | | | | | | | | Remove QMP PHY type-specific headers inclusion from the common header and move them to the specific PHY drivers to cleanup the namespaces used by different drivers. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-14-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-usb: fix regs layout arraysDmitry Baryshkov2023-01-121-11/+13
| | | | | | | | | | Drop qcm2290_usb3phy_regs_layout, it is a duplicate of qmp_v3_usb3phy_regs_layout. Introduce qmp_v5_usb3phy_regs_layout to be used for sm8350 and sc8280xp. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-13-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-usb: rework regs layout arraysDmitry Baryshkov2023-01-122-26/+29
| | | | | | | | | | | | | Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-12-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-usb: remove QPHY_PCS_MISC_TYPEC_CTRL regDmitry Baryshkov2023-01-121-3/+0
| | | | | | | | | The QPHY_PCS_MISC_TYPEC_CTRL register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-11-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-usb: remove QPHY_PCS_LFPS_RXTERM_IRQ_STATUS regDmitry Baryshkov2023-01-122-6/+1
| | | | | | | | | The QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-10-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: rename regs layout arraysDmitry Baryshkov2023-01-122-16/+21
| | | | | | | | Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-9-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: rework regs layout arraysDmitry Baryshkov2023-01-123-9/+17
| | | | | | | | | | Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-8-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: split UFS-specific v2 PCS registers to a separate headerDmitry Baryshkov2023-01-124-20/+30
| | | | | | | | | Follow other QMP headers, split and rename UFS-specific PCS registers to ease comparing regs differences. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-pcie-msm8996: rework regs layout arraysDmitry Baryshkov2023-01-121-3/+3
| | | | | | | | | | | | | Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-6-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-pcie: rename regs layout arraysDmitry Baryshkov2023-01-122-26/+30
| | | | | | | | Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-5-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-pcie: rework regs layout arraysDmitry Baryshkov2023-01-122-16/+20
| | | | | | | | Use symbolic names for the values inside reg layout arrays. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-4-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp: remove duplicate v5_5nm register definitionsDmitry Baryshkov2023-01-121-5/+0
| | | | | | | | Remove duplicate defines from phy-qcom-qmp-qserdes-txrx-v5_5nm.h Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp: fix typo in QSERDES_COM_CMN_RSVD5 valueDmitry Baryshkov2023-01-121-1/+1
| | | | | | | | Fix typo in QSERDES_COM_CMN_RSVD5 register definition. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221110192248.873973-2-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp-ufs: provide symbol clocksDmitry Baryshkov2023-01-121-0/+57
| | | | | | | | | | Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src, ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock provider to let other devices link these clocks through the DT. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221123104443.3415267-3-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-02 03:23:06 +0000