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* phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I2021-03-311-1/+6
| | | | | | | | | | | | | | | Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Cc: <stable@vger.kernel.org> # v5.4+ Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qcom-qmp: add hbr3_hbr2 voltage and premphasis swing tableKuogee Hsieh2021-03-301-2/+21
| | | | | | | | | | | Add hbr3_hbr2 voltage and premphasis swing table to support HBR3 link rate. Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615914761-12300-1-git-send-email-khsieh@codeaurora.org Fixes: 52e013d0bffa ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy") Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ingenic: Fix a typo in ingenic_usb_phy_probe()Wei Yongjun2021-03-301-2/+2
| | | | | | | | | | | | Fix the return value check typo which testing the wrong variable in ingenic_usb_phy_probe(). Fixes: 31de313dfdcf ("PHY: Ingenic: Add USB PHY driver using generic PHY framework.") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20210305034933.3240914-1-weiyongjun1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ralink: phy-mt7621-pci: fix return value check in mt7621_pci_phy_probe()Wei Yongjun2021-03-301-2/+2
| | | | | | | | | | | | Fix the return value check which testing the wrong variable in mt7621_pci_phy_probe(). Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210305034931.3237558-1-weiyongjun1@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: marvell: ARMADA375_USBCLUSTER_PHY should not default to y, unconditionallyGeert Uytterhoeven2021-03-301-2/+2
| | | | | | | | | | | Merely enabling CONFIG_COMPILE_TEST should not enable additional code. To fix this, restrict the automatic enabling of ARMADA375_USBCLUSTER_PHY to MACH_ARMADA_375, and ask the user in case of compile-testing. Fixes: eee47538ec1f2619 ("phy: add support for USB cluster on the Armada 375 SoC") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210208150252.424706-1-geert+renesas@glider.be Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ti: j721e-wiz: add missing call to of_node_put()Yang Li2021-03-301-0/+1
| | | | | | | | | | | | | | | In one of the error paths of the for_each_child_of_node() loop in of_property_read_u32, add missing call to of_node_put(). Fix the following coccicheck warning: ./drivers/phy/ti/phy-j721e-wiz.c:786:1-23: WARNING: Function "for_each_child_of_node" should have of_node_put() before return around line 795. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Link: https://lore.kernel.org/r/1614244674-66556-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ralink: phy-mt7621-pci: fix XTAL bitmaskSergio Paracuellos2021-03-301-1/+1
| | | | | | | | | | | | When this was rewriten to get mainlined and start to use 'linux/bitfield.h' headers, XTAL_MASK was wrong. It must mask three bits but only two were used. Hence properly fix it to make things work. Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210302105412.16221-1-sergio.paracuellos@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Update PCIe + USB config for correct PLL1 clockSwapnil Jakhade2021-03-301-16/+31
| | | | | | | | | | Update PCIe + USB register sequences for correct PLL1 clock configuration. Also, update sequences for other USB configurations with dependent changes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-5-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Update SGMII/QSGMII configuration specific to TIKishon Vijay Abraham I2021-03-301-14/+44
| | | | | | | | | Update SGMII/QSGMII configuration specific to TI. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1614838096-32291-4-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ti: j721e-wiz: Add support for configuring QSGMIIKishon Vijay Abraham I2021-03-301-2/+62
| | | | | | | | | Configure MAC clock dividers required for QSGMII to be functional. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/1614838096-32291-3-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Update PCIe + QSGMII config for correct PLL1 clockSwapnil Jakhade2021-03-301-28/+49
| | | | | | | | | | | | | | For PCIe + QSGMII configuration where QSGMII was using PLL1 and was expecting 10GHz clock, configuration was giving 8GHz clock. Update register sequences to get correct PLL1 configuration. Also, update single link PCIe and single link SGMII/QSGMII configurations with related changes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/1614838096-32291-2-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: cadence-torrent: Add support to drive refclk outKishon Vijay Abraham I2021-03-302-3/+186
| | | | | | | | | | | | | | | cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. Model this derived reference clock as a "clock" so that platforms like AM642 EVM can enable it. This is used by PCIe to use the same refclk both in local SERDES and remote device. Add support here to drive refclk out. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210310120840.16447-7-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ti: j721e-wiz: Enable reference clock output in cmn_refclk_<p/m>Kishon Vijay Abraham I2021-03-301-0/+89
| | | | | | | | | | | | | cmn_refclk_<p/m> lines in Torrent SERDES is used for connecting external reference clock. cmn_refclk_<p/m> can also be configured to output the reference clock. In order to drive the refclk out from the SERDES (Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ. Model PHY_EN_REFCLK as a clock, so that platforms like AM642 EVM can enable it. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ti: j721e-wiz: Model the internal clocks without device tree inputKishon Vijay Abraham I2021-03-301-5/+139
| | | | | | | | | | | | | | | | | | commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled the internal clocks depending on the subnodes that are populated in device tree. However recent discussions in the mailing list [1] suggested to just add #clock cells in the parent DT node and model the clocks within the driver. Model the mux clocks without device tree input for AM64x SoC. Don't remove the earlier design since DT nodes for J7200 and J721e are already upstreamed. [1] -> http://lore.kernel.org/r/20210108025943.GA1790601@robh.at.kernel.org Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-5-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ti: j721e-wiz: Configure full rate divider for AM64Kishon Vijay Abraham I2021-03-301-3/+36
| | | | | | | | | | The frequency of the txmclk between PCIe and SERDES has changed to 250MHz from 500MHz. Configure full rate divider for AM64 accordingly. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ti: j721e-wiz: Delete "clk_div_sel" clk provider during cleanupKishon Vijay Abraham I2021-03-301-0/+6
| | | | | | | | | | | | commit 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") modeled both MUX clocks and DIVIDER clocks in wiz. However during cleanup, it removed only the MUX clock provider. Remove the DIVIDER clock provider here. Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: ti: j721e-wiz: Remove "regmap_field" from wiz_clk_{mux|div}_selKishon Vijay Abraham I2021-03-301-41/+34
| | | | | | | | | | | | | | | Both "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" are static data that is common for all wiz instances. Including "struct regmap_field" for each of the wiz instances can yield undesirable results. Move "struct regmap_field" out of "struct wiz_clk_div_sel" and "struct wiz_clk_mux_sel" and make them point to constant data. So far no issues are observed since both these structures are not accessed outside the probe. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210310120840.16447-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* devicetree/bindings: add support for CP110 UTMI PHYKonstantin Porotchkin2021-03-301-0/+109
| | | | | | | | | Add DTS binding for Marvell CP110 UTMI PHY Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210307163343.25684-4-kostap@marvell.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: convert phy-mvebu-utmi to YAML schemaKonstantin Porotchkin2021-03-302-38/+57
| | | | | | | | | The new file name is marvell,armada-3700-utmi-phy.yaml Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210307163343.25684-3-kostap@marvell.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* drivers: phy: add support for Armada CP110 UTMI PHYKonstantin Porotchkin2021-03-303-0/+393
| | | | | | | | | | | | | | | Add support for Marvell CP110 UTMI PHY driver allowing the USB2 port configuration independently from the boot loader setup. The CP110/CP115 dies have 2 UTMI PHYs that could be connected to two USB host controllers or to single USB device controller. Since there is only one USB device controller on die, only one of the UTMI PHYs could work in USB device mode. The CONFIG_PHY_MVEBU_CP110_UTMI should be enabled for usage of this driver. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Link: https://lore.kernel.org/r/20210307163343.25684-2-kostap@marvell.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: qualcomm: remove duplicate argumentZhang Yunkai2021-03-251-2/+2
| | | | | | | | 'HSUSB_CTRL_DPSEHV_CLAMP' in 'val' is duplicated. Signed-off-by: Zhang Yunkai <zhang.yunkai@zte.com.cn> Link: https://lore.kernel.org/r/20210319113612.494623-1-zhang.yunkai@zte.com.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: intel: Fix a typoBhaskar Chowdhury2021-03-251-1/+1
| | | | | | | | s/subsytem/subsystem/ Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Link: https://lore.kernel.org/r/20210320204055.26107-1-unixbhaskar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SC7280Sandeep Maheswaram2021-03-251-0/+1
| | | | | | | | | | Add the compatible string for sc7280 SoC from Qualcomm Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615978901-4202-3-git-send-email-sanm@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: mediatek: tphy: change patternPropertiesChunfeng Yun2021-03-251-1/+1
| | | | | | | | | | | The phy may be named as pcie-phy when the T-PHY only supports PCIe mode, it's also the similar case for SATA, named as sata-phy. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20210316092232.9806-4-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: mediatek: hdmi-phy: modify compatible itemsChunfeng Yun2021-03-251-4/+7
| | | | | | | | | | | | | | | mt7623-hdmi-tx is compatible to mt2701-hdmi-tx, and the compatible "mediatek,mt7623-hdmi-tx" is not supported in driver, in fact uses "mediatek,mt2701-hdmi-tx" instead on MT7623, so changes the compatible items to make dependence clear. Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20210316092232.9806-3-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: mediatek: dsi-phy: modify compatible dependenceChunfeng Yun2021-03-251-5/+8
| | | | | | | | | | | | | | mt7623-mipi-tx is compatible to mt2701-mipi-tx, and use "mediatek,mt2701-mipi-tx" instead on MT7623, so modify the compatible items to make dependence clear. Cc: Chun-Kuang Hu <chunkuang.hu@kernel.org> Cc: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20210316092232.9806-2-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: Add Sparx5 ethernet serdes PHY driverSteen Hegelund2021-03-177-0/+5331
| | | | | | | | | | | | Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G interfaces available in the Sparx5 SoC. Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20210218161451.3489955-4-steen.hegelund@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* phy: Add media type and speed serdes configuration interfacesSteen Hegelund2021-03-172-0/+56
| | | | | | | | | | | | | | Provide new phy configuration interfaces for media type and speed that allows e.g. PHYs used for ethernet to be configured with this information. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-By: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210218161451.3489955-3-steen.hegelund@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: Add sparx5-serdes bindingsSteen Hegelund2021-03-171-0/+100
| | | | | | | | | | | | Document the Sparx5 ethernet serdes phy driver bindings. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20210218161451.3489955-2-steen.hegelund@microchip.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: Add compatible for Mediatek MT8195Seiya Wang2021-03-171-0/+1
| | | | | | | | | This commit adds dt-binding documentation of UFS M-Phy for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> Link: https://lore.kernel.org/r/20210316111443.3332-9-seiya.wang@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dt-bindings: phy: Add compatible for Mediatek MT8195Seiya Wang2021-03-171-0/+1
| | | | | | | | | This commit adds dt-binding documentation of T-Phy for Mediatek MT8195 SoC Platform. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> Link: https://lore.kernel.org/r/20210316111443.3332-8-seiya.wang@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'ti-serdes-for-5.13' into nextVinod Koul2021-03-175-3/+49
|\ | | | | | | TI Serdes changes for 5.13
| * dt-bindings: ti-serdes-mux: Add defines for AM64 SoCKishon Vijay Abraham I2021-03-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210310112745.3445-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dt-bindings: phy: cadence-torrent: Add binding for refclk driverKishon Vijay Abraham I2021-03-172-3/+19
| | | | | | | | | | | | | | | | | | | | Add binding for refclk driver used to route the refclk out of torrent SERDES. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210310112745.3445-3-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES WrapperKishon Vijay Abraham I2021-03-172-0/+25
| | | | | | | | | | | | | | | | | | Add bindings for AM64 SERDES Wrapper. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210310112745.3445-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dt-bindings: phy: brcm,brcmstb-usb-phy: add power-domainsRafał Miłecki2021-03-151-0/+3
| | | | | | | | | | | | | | | | | | | | On BCM4908 USB PHY is managed using power controller so it needs describing properly using the power-domains. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210309182616.25783-1-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: phy-brcm-usb: select SOC_BRCMSTB on brcmstb onlyRafał Miłecki2021-03-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | phy-brcm-usb has some conditional init code required on selected brcmstb devices. Execution of that code depends on family / product detected by brcmstb soc code. For ARCH_BCM4908 brcmstb soc code always return 0 values as ids. Don't bother selecting & compiling that redundant driver. Depends-on: 149ae80b1d50 ("soc: bcm: brcmstb: add stubs for getting platform IDs") Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210305152406.2588-1-zajec5@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: qcom-usb-hs: Fix fall-through warnings for ClangGustavo A. R. Silva2021-03-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a break statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Link: https://lore.kernel.org/r/20210305100219.GA142595@embeddedor Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: ti: j721e-wiz: add missing of_node_putJunlin Yang2021-03-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | Fix OF node leaks by calling of_node_put in for_each_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210216082739.1414-1-angkery@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: rockchip-typec: add missing of_node_putJunlin Yang2021-03-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | Fix OF node leaks by calling of_node_put in for_each_available_child_of_node when the cycle returns. Generated by: scripts/coccinelle/iterators/for_each_child.cocci Signed-off-by: Junlin Yang <yangjunlin@yulong.com> Link: https://lore.kernel.org/r/20210216084847.1544-1-angkery@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: stm32: register usbphyc as clock provider of ck_usbo_48m clockAmelie Delaunay2021-03-152-0/+66
| | | | | | | | | | | | | | | | | | | | | | ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Link: https://lore.kernel.org/r/20210208114659.15269-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells propertyAmelie Delaunay2021-03-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | usbphyc provides a unique clock called ck_usbo_48m. STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation. ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210208114659.15269-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | phy: tusb1210: use bitmasks to set VENDOR_SPECIFIC2Liam Beguin2021-03-121-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Start by reading the content of the VENDOR_SPECIFIC2 register and update each bit field based on device properties when defined. The use of bit masks prevents fields from overriding each other and enables users to clear bits which are set by default, like datapolarity in this instance. Signed-off-by: Liam Beguin <lvb@xiphos.com> Link: https://lore.kernel.org/r/20201211191241.21306-1-liambeguin@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | MAINTAINERS: Add linux-phy list and patchworkVinod Koul2021-03-121-1/+2
|/ | | | | | | Linux-phy subsystem gained mailing list and a patchwork instance. Add the details to MAINTAINERS file Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Linux 5.12-rc2v5.12-rc2Linus Torvalds2021-03-051-1/+1
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* Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdmaLinus Torvalds2021-03-058-62/+76
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull rdma fixes from Jason Gunthorpe: "Nothing special here, though Bob's regression fixes for rxe would have made it before the rc cycle had there not been such strong winter weather! - Fix corner cases in the rxe reference counting cleanup that are causing regressions in blktests for SRP - Two kdoc fixes so W=1 is clean - Missing error return in error unwind for mlx5 - Wrong lock type nesting in IB CM" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: RDMA/rxe: Fix errant WARN_ONCE in rxe_completer() RDMA/rxe: Fix extra deref in rxe_rcv_mcast_pkt() RDMA/rxe: Fix missed IB reference counting in loopback RDMA/uverbs: Fix kernel-doc warning of _uverbs_alloc RDMA/mlx5: Set correct kernel-doc identifier IB/mlx5: Add missing error code RDMA/rxe: Fix missing kconfig dependency on CRYPTO RDMA/cm: Fix IRQ restore in ib_send_cm_sidr_rep
| * RDMA/rxe: Fix errant WARN_ONCE in rxe_completer()Bob Pearson2021-03-051-32/+23
| | | | | | | | | | | | | | | | | | | | | | | | In rxe_comp.c in rxe_completer() the function free_pkt() did not clear skb which triggered a warning at 'done:' and could possibly at 'exit:'. The WARN_ONCE() calls are not actually needed. The call to free_pkt() is moved to the end to clearly show that all skbs are freed. Fixes: 899aba891cab ("RDMA/rxe: Fix FIXME in rxe_udp_encap_recv()") Link: https://lore.kernel.org/r/20210304192048.2958-1-rpearson@hpe.com Signed-off-by: Bob Pearson <rpearsonhpe@gmail.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
| * RDMA/rxe: Fix extra deref in rxe_rcv_mcast_pkt()Bob Pearson2021-03-051-24/+35
| | | | | | | | | | | | | | | | | | | | | | rxe_rcv_mcast_pkt() dropped a reference to ib_device when no error occurred causing an underflow on the reference counter. This code is cleaned up to be clearer and easier to read. Fixes: 899aba891cab ("RDMA/rxe: Fix FIXME in rxe_udp_encap_recv()") Link: https://lore.kernel.org/r/20210304192048.2958-1-rpearson@hpe.com Signed-off-by: Bob Pearson <rpearsonhpe@gmail.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
| * RDMA/rxe: Fix missed IB reference counting in loopbackBob Pearson2021-03-051-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | When the noted patch below extending the reference taken by rxe_get_dev_from_net() in rxe_udp_encap_recv() until each skb is freed it was not matched by a reference in the loopback path resulting in underflows. Fixes: 899aba891cab ("RDMA/rxe: Fix FIXME in rxe_udp_encap_recv()") Link: https://lore.kernel.org/r/20210304192048.2958-1-rpearson@hpe.com Signed-off-by: Bob Pearson <rpearsonhpe@gmail.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
| * RDMA/uverbs: Fix kernel-doc warning of _uverbs_allocLeon Romanovsky2021-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | Fix the following W=1 compilation warning: drivers/infiniband/core/uverbs_ioctl.c:108: warning: expecting prototype for uverbs_alloc(). Prototype was for _uverbs_alloc() instead Fixes: 461bb2eee4e1 ("IB/uverbs: Add a simple allocator to uverbs_attr_bundle") Link: https://lore.kernel.org/r/20210302074214.1054299-3-leon@kernel.org Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-06 19:26:32 +0000