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* clocksource/drivers/timer-ti-dm: Add flag to detect omap1Tony Lindgren2022-09-201-3/+6
| | | | | | | | | | Let's make it clear that some features need to be tested currently on omap1. Only omap1 still uses platform_data. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-9-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/timer-ti-dm: Move struct omap_dm_timer fields to driverTony Lindgren2022-09-202-91/+170
| | | | | | | | | | | | | | | | | | | There is no longer any need to expose the elements of struct omap_dm_timer outside the driver. The pwm and remoteproc drivers just use struct omap_dm_timer as a cookie. Let's move the elements of struct omap_dm_timer into struct dmtimer that is private to the driver. To do this, we mostly rename omap_dm_timer to dmtimer in the driver. We keep omap_dm_timer only for the exposed functions in the platform_data for the pwm and remoteproc drivers. Let's also add a note about not using the exposed functions internally as those will get deprecated eventually in favor of Linux generic frameworks. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-8-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/timer-ti-dm: Use runtime PM directly and check errorsTony Lindgren2022-09-201-26/+91
| | | | | | | | | | | | | | Use pm_runtime_resume_and_get() and check for a possible error returned. We want to do this as omap_dm_timer_enable() and omap_dm_timer_disable() are exposed to the pwm and remoteproc drivers, and in the following patch we turn struct omap_dm_timer into a cookie used by the exposed functions only. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-7-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/timer-ti-dm: Move private defines to the driverTony Lindgren2022-09-202-62/+62
| | | | | | | | | These defines are only used by timer-ti-dm driver. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-6-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/timer-ti-dm: Simplify register access furtherTony Lindgren2022-09-202-17/+17
| | | | | | | | | | | Let's unify register access and use dmtimer_read() and dmtimer_write() also for the timer revision specific registers like we now do for the shread registers. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-5-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/timer-ti-dm: Simplify register writes with dmtimer_write()Tony Lindgren2022-09-201-54/+44
| | | | | | | | | | | | | | | We can simplify register write access by checking for the register write posted mode in the write function. This way we can combine the functions for __omap_dm_timer_write() and omap_dm_timer_write_reg() into a single function dmtimer_write(). We update the shared register access first, the timer revision specific register access will be updated in a later patch. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-4-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/timer-ti-dm: Simplify register reads with dmtimer_read()Tony Lindgren2022-09-201-48/+40
| | | | | | | | | | | | | | | We can simplify register read access by checking for the register write posted mode in the read function. This way we can combine the functions for __omap_dm_timer_read() and omap_dm_timer_read_reg() into a single function dmtimer_read(). We update the shared register access first, the timer revision specific register access will be updated in a later patch. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-3-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/timer-ti-dm: Drop unused functionsTony Lindgren2022-09-202-58/+0
| | | | | | | | | We still have some unused functions left, let's drop them. Signed-off-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Janusz Krzysztofik <jmkrzyszt@gmail.com> Link: https://lore.kernel.org/r/20220815131250.34603-2-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/timer-gxp: Add missing error handling in gxp_timer_probeLin Yujun2022-09-201-1/+6
| | | | | | | | | | Add platform_device_put() to make sure to free the platform device in the event platform_device_add() fails. Fixes: 5184f4bf151b ("clocksource/drivers/timer-gxp: Add HPE GXP Timer") Signed-off-by: Lin Yujun <linyujun809@huawei.com> Link: https://lore.kernel.org/r/20220914033018.97484-1-linyujun809@huawei.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/arm_arch_timer: Fix handling of ARM erratum 858921Kunkun Jiang2022-09-201-0/+2
| | | | | | | | | | | | | | | | | | | | The commit a38b71b0833e ("clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL") moves the programming of the timers from the countdown timer (TVAL) over to the comparator (CVAL). This makes it necessary to read the counter when programming next event. However, the workaround of Cortex-A73 erratum 858921 does not set the corresponding set_next_event_phys and set_next_event_virt. Add the appropriate hooks to apply the erratum mitigation when programming the next timer event. Fixes: a38b71b0833e ("clocksource/drivers/arm_arch_timer: Move system register timer programming over to CVAL") Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com> Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Link: https://lore.kernel.org/r/20220914061424.1260-1-jiangkunkun@huawei.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/exynos_mct: Enable building on ARTPECVincent Whitchurch2022-09-201-1/+1
| | | | | | | | | This timer block is used on ARTPEC-8. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220609112738.359385-5-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/exynos_mct: Support local-timers propertyVincent Whitchurch2022-09-201-6/+56
| | | | | | | | | | If the device tree indicates that the hardware requires that the processor only use certain local timers, respect that. Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220609112738.359385-4-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/exynos_mct: Support frc-shared propertyVincent Whitchurch2022-09-201-3/+18
| | | | | | | | | | | When the FRC is shared with another main processor, the other processor is assumed to have started it and this processor should not write to the global registers. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220609112738.359385-3-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* dt-bindings: timer: exynos4210-mct: Add ARTPEC-8 MCT supportVincent Whitchurch2022-09-201-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARTPEC-8 has an MCT with 4 global and 8 local timer interrupts. The SoC has a quad-core Cortex-A53 and a single-core Cortex-A5 which share one MCT with one global and eight local timers. The Cortex-A53 and Cortex-A5 do not have cache-coherency between them, and therefore run two separate kernels. The Cortex-A53 boots first and starts the global free-running counter and also registers a clock events device using the global timer. (This global timer clock events is usually replaced by arch timer clock events for each of the cores.) When the A5 boots (via the A53), it should not use the global timer interrupts or write to the global timer registers. This is because even if there are four global comparators, the control bits for all four are in the same registers, and we would need to synchronize between the cpus. Instead, the global timer FRC (already started by the A53) should be used as the clock source, and one of the local timers which are not used by the A53 can be used for clock events on the A5. To support this hardware, add a compatible for the MCT as well as two new properties to describe the hardware-mandated sharing of the FRC and dedicating local timers to specific processors. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220609112738.359385-2-vincent.whitchurch@axis.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/sun4i: Add definition of clear interruptVictor Hassan2022-09-201-1/+2
| | | | | | | | | | To prevent misunderstanding, use TIMER_IRQ_CLEAR instead of TIMER_IRQ_EN in function sun4i_timer_clear_interrupt. Signed-off-by: Victor Hassan <victor@allwinnertech.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220906052056.43404-1-victor@allwinnertech.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* clocksource/drivers/renesas-ostm: Add support for RZ/V2L SoCLad Prabhakar2022-09-071-1/+1
| | | | | | | | | | | | | | The OSTM block is identical on Renesas RZ/G2L and RZ/V2L SoC's, so instead of adding dependency for each SoC's add dependency on ARCH_RZG2L. The ARCH_RZG2L config option is already selected by ARCH_R9A07G044 and ARCH_R9A07G054. With the above change OSTM will be enabled on RZ/V2L SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220907080056.3460-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* dt-bindings: timer: renesas,tmu: Add r8a779f0 supportWolfram Sang2022-08-191-0/+1
| | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220726205858.1199-1-wsa+renesas@sang-engineering.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* dt-bindings: timer: Add compatible for MediaTek MT8188Johnson Wang2022-08-191-0/+1
| | | | | | | | | | Add dt-binding documentation of timer for MediaTek MT8188 SoC platform. Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220818124602.20394-1-johnson.wang@mediatek.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* wait: Fix __wait_event_hrtimeout for RT/DL tasksJuri Lelli2022-07-281-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes to hrtimer mode (potentially made by __hrtimer_init_sleeper on PREEMPT_RT) are not visible to hrtimer_start_range_ns, thus not accounted for by hrtimer_start_expires call paths. In particular, __wait_event_hrtimeout suffers from this problem as we have, for example: fs/aio.c::read_events wait_event_interruptible_hrtimeout __wait_event_hrtimeout hrtimer_init_sleeper_on_stack <- this might "mode |= HRTIMER_MODE_HARD" on RT if task runs at RT/DL priority hrtimer_start_range_ns WARN_ON_ONCE(!(mode & HRTIMER_MODE_HARD) ^ !timer->is_hard) fires since the latter doesn't see the change of mode done by init_sleeper Fix it by making __wait_event_hrtimeout call hrtimer_sleeper_start_expires, which is aware of the special RT/DL case, instead of hrtimer_start_range_ns. Reported-by: Bruno Goncalves <bgoncalv@redhat.com> Signed-off-by: Juri Lelli <juri.lelli@redhat.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Daniel Bristot de Oliveira <bristot@kernel.org> Reviewed-by: Valentin Schneider <vschneid@redhat.com> Link: https://lore.kernel.org/r/20220627095051.42470-1-juri.lelli@redhat.com
* Merge tag 'timers-v5.20-rc1' of ↵Thomas Gleixner2022-07-2817-191/+893
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clockevent/source updates from Daniel Lezcano: - Add the missing DT bindings for the MTU nomadik timer (Linus Walleij) - Fix grammar typo in the ARM global timer Kconfig option (Randy Dunlap) - Add the tegra186 timer and use it on the tegra234 board (Thierry Reding) - Add the 'CPUXGPT' CPU timer for Mediatek MT6795 and implement a workaround to overcome an ATF bug where the timer is not correctly initialized (AngeloGioacchino Del Regno) - Rework the suspend/resume approach to enable the feature on the timer even it is not an active clock and fix a compilation warning (Claudiu Beznea) - Add the Add R-Car Gen4 timer support along with the DT bindings (Wolfram Sang) - Add compatible for ti,am654-timer to support AM6 SoC (Tony Lindgren) - Fix Kconfig option to put it back to 'bool' instead of 'tristate' for the tegra186 (Daniel Lezcano) - Sort 'family,type' DT bindings for the Renesas timers (Geert Uytterhoeven) - Add compatible 'allwinner,sun20i-d1-timer' for Allwinner D1 (Samuel Holland) - Remove unnecessary (void*) conversions for sun4i (XU pengfei) - Remove unnecessary (void*) conversions for sun5i (Li zeming) Link: https://lore.kernel.org/all/7472984e-f502-5f27-82bf-070127dd85a5@linaro.org
| * clocksource/drivers/sun5i: Remove unnecessary (void*) conversionsLi zeming2022-07-271-1/+1
| | | | | | | | | | | | | | | | Remove unnecessary void* type castings. Signed-off-by: Li zeming <zeming@nfschina.com> Link: https://lore.kernel.org/r/20220727083751.5540-1-zeming@nfschina.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * dt-bindings: timer: allwinner,sun4i-a10-timer: Add D1 compatibleSamuel Holland2022-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | Allwinner D1 contains the usual sun4i MMIO timer device. It contains two timers like other recent SoCs, so it is compatible with the A23 variant. Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220725051715.56427-1-samuel@sholland.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * dt-bindings: timer: ingenic,tcu: use absolute path to other schemaKrzysztof Kozlowski2022-07-271-2/+2
| | | | | | | | | | | | | | | | | | Absolute path to other DT schema is preferred over relative one. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20220726115937.101432-1-krzysztof.kozlowski@linaro.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/sun4i: Remove unnecessary (void*) conversionsXU pengfei2022-07-271-1/+1
| | | | | | | | | | | | | | | | Remove unnecessary void* type casting. Signed-off-by: XU pengfei <xupengfei@nfschina.com> Link: https://lore.kernel.org/r/20220720020735.3771-1-xupengfei@nfschina.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * dt-bindings: timer: renesas,cmt: Fix R-Car Gen4 fall-outGeert Uytterhoeven2022-07-271-6/+8
| | | | | | | | | | | | | | | | | | | | | | Restore sort order (by family, followed by type). Update the conditional sections specifying the number of interrupts. Fixes: 525b296185b4b0ab ("dt-bindings: timer: renesas,cmt: Add r8a779f0 and generic Gen4 CMT support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/2e3863ae32e17d49f41111580f195dd34e2b769d.1658303544.git.geert+renesas@glider.be Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/tegra186: Put Kconfig option 'tristate' to 'bool'Daniel Lezcano2022-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | The clocksources are built-in, they are not modules. We don't know if the core time framework is ready for clockevents / clocksources as modules. Revert back this option to 'bool'. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lore.kernel.org/r/20220718213657.1303538-1-daniel.lezcano@linaro.org
| * clocksource/drivers/timer-ti-dm: Make driver selection bool for TI K3Tony Lindgren2022-07-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clocksource drivers do not currently have loadable modules as pointed out by Daniel Lezcano <daniel.lezcano@linaro.org>. Let's reconsider this later on once timer removal discussion has been done, and set timer-ti-dm to bool for TI K3 SoC. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220523151448.23732-1-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/timer-ti-dm: Add compatible for am6 SoCsTony Lindgren2022-07-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add compatible for ti,am654-timer to support the timers. For example, am654 has four timers in the MCU domain and 12 timers in the MAIN domain. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220408101715.43697-4-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/timer-ti-dm: Make timer selectable for ARCH_K3Tony Lindgren2022-07-273-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's make timer-ti-dm selectable for ARCH_K3, and add a separate option for OMAP_DM_SYSTIMER as there should be no need for it on ARCH_K3. For older TI SoCs, we are already selecting OMAP_DM_TIMER in arch/arm/mach-omap*/Kconfig. For mach-omap2, we need to now also select OMAP_DM_SYSTIMER. Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220408101715.43697-3-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/timer-ti-dm: Move inline functions to driver for am6Tony Lindgren2022-07-272-144/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The __omap_dm_timer_* inline functions in the header are no longer needed outside the driver, and the header ifdefs prevent the driver working for ARCH_K3. Let's move the inline functions to the driver and drop the ifdefs and drop the unused functions __omap_dm_timer_override_errata() and __omap_dm_timer_load_start(). Cc: Keerthy <j-keerthy@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20220408101715.43697-2-tony@atomide.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/sh_cmt: Add R-Car Gen4 supportWolfram Sang2022-07-181-0/+8
| | | | | | | | | | | | | | | | | | Add support for the R-Car Gen4 CMT types 0/1 which are the same as in the previous two generations. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220713100603.3391-4-wsa+renesas@sang-engineering.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * dt-bindings: timer: renesas,cmt: R-Car V3U is R-Car Gen4Wolfram Sang2022-07-181-2/+2
| | | | | | | | | | | | | | | | | | | | Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence move its compatible value to the R-Car Gen4 section. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220713100603.3391-3-wsa+renesas@sang-engineering.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * dt-bindings: timer: renesas,cmt: Add r8a779f0 and generic Gen4 CMT supportWolfram Sang2022-07-181-0/+10
| | | | | | | | | | | | | | Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220713100603.3391-2-wsa+renesas@sang-engineering.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/timer-microchip-pit64b: Fix compilation warningsClaudiu Beznea2022-07-161-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | Fix the following compilation warnings: timer-microchip-pit64b.c:68: warning: cannot understand function prototype: 'struct mchp_pit64b_clkevt ' timer-microchip-pit64b.c:82: warning: cannot understand function prototype: 'struct mchp_pit64b_clksrc ' timer-microchip-pit64b.c:283: warning: Function parameter or member 'timer' not described in 'mchp_pit64b_init_mode' timer-microchip-pit64b.c:283: warning: Function parameter or member 'max_rate' not described in 'mchp_pit64b_init_mode' Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609094041.1796372-4-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/timer-microchip-pit64b: Use mchp_pit64b_{suspend, resume}Claudiu Beznea2022-07-161-19/+5
| | | | | | | | | | | | | | | | | | | | | | | | Use mchp_pit64b_suspend() and mchp_pit64b_resume() to disable or enable timers clocks on init and remove specific clk_prepare_{disable, enable} calls. This is ok also for clockevent timer as proper clock enable, disable is done on .set_state_oneshot, .set_state_periodic, .set_state_shutdown calls. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609094041.1796372-3-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/timer-microchip-pit64b: Remove suspend/resume ops for ceClaudiu Beznea2022-07-161-14/+16
| | | | | | | | | | | | | | | | | | | | | | Remove suspend and resume ops for clockevent and add set_state_oneshot() instead. Along with this mchp_pit64b_{suspend, resume}() were called on proper function to disable/enable clocks. This will allow disabling clocks for clockevent in case it is not selected as active clockevent. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609094041.1796372-2-claudiu.beznea@microchip.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * thermal/drivers/rcar_gen3_thermal: Add r8a779f0 supportWolfram Sang2022-07-161-0/+4
| | | | | | | | | | | | | | | | | | | | Add support for R-Car S4. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20220705195520.2581-1-wsa+renesas@sang-engineering.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/timer-mediatek: Implement CPUXGPT timersAngeloGioacchino Del Regno2022-07-161-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some MediaTek platforms with a buggy TrustZone ATF firmware will not initialize the AArch64 System Timer correctly: in these cases, the System Timer address is correctly programmed, as well as the CNTFRQ_EL0 register (reading 13MHz, as it should be), but the assigned hardware timers are never started before (or after) booting Linux. In this condition, any call to function get_cycles() will be returning zero, as CNTVCT_EL0 will always read zero. One common critical symptom of that is trying to use the udelay() function (calling __delay()), which executes the following loop: start = get_cycles(); while ((get_cycles() - start) < cycles) cpu_relax(); which, when CNTVCT_EL0 always reads zero, translates to: while((0 - 0) < 0) ==> while(0 < 0) ... generating an infinite loop, even though zero is never less than zero, but always equal to it (this has to be researched, but it's out of the scope of this commit). To fix this issue on the affected MediaTek platforms, the solution is to simply start the timers that are designed to be System Timer(s). These timers, downstream, are called "CPUXGPT" and there is one timer per CPU core; luckily, it is not necessary to set a start bit on each CPUX General Purpose Timer, but it's conveniently enough to: - Set the clock divider (input = 26MHz, divider = 2, output = 13MHz); - Set the ENABLE bit on a global register (starts all CPUX timers). The only small hurdle with this setup is that it's all done through the MCUSYS wrapper, where it is needed, for each read or write, to select a register address (by writing it to an index register) and then to perform any R/W on a "CON" register. For example, writing "0x1" to the CPUXGPT register offset 0x4: - Write 0x4 to mcusys INDEX register - Write 0x1 to mcusys CON register Reading from CPUXGPT register offset 0x4: - Write 0x4 to mcusys INDEX register - Read mcusys CON register. Finally, starting this timer makes platforms affected by this issue to work correctly. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20220613133819.35318-3-angelogioacchino.delregno@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * dt-bindings: timer: mediatek: Add CPUX System Timer and MT6795 compatibleAngeloGioacchino Del Regno2022-07-161-1/+5
| | | | | | | | | | | | | | | | | | | | | | Document the "CPUXGPT" CPU General Purpose Timer, used as ARM/ARM64 System Timer on MediaTek platforms and add the MT6795 compatible for it. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/20220613133819.35318-2-angelogioacchino.delregno@collabora.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/timer-tegra186: Add support for Tegra234 SoCKartik2022-07-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | The timer IP block present on Tegra234 SoC supports watchdog timer functionality that can be used to recover from system hangs. The watchdog timer uses a timer in the background for countdown. Signed-off-by: Kartik <kkartik@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/1656922422-25823-4-git-send-email-kkartik@nvidia.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource: Add Tegra186 timers supportThierry Reding2022-07-163-0/+517
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently this only supports a single watchdog, which uses a timer in the background for countdown. Eventually the timers could be used for various time-keeping tasks, but by default the architected timer will already provide that functionality. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kartik <kkartik@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/1656922422-25823-3-git-send-email-kkartik@nvidia.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * clocksource/drivers/arm_global_timer: Fix Kconfig "its" grammarRandy Dunlap2022-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Use the possessive "its" instead of the contraction "it's" where appropriate. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Patrice Chotard <patrice.chotard@foss.st.com> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220715015852.12523-1-rdunlap@infradead.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| * dt-bindings: timer: Add Nomadik MTU bindingLinus Walleij2022-06-141-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | The Nomadik MTU timer has been used in devicetrees forever but somehow we missed to add a binding for it. Fix it by simply adding it. Cc: Lee Jones <lee.jones@linaro.org> Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220526213621.373727-1-linus.walleij@linaro.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* | Linux 5.19-rc8v5.19-rc8Linus Torvalds2022-07-241-1/+1
| |
* | certs: make system keyring depend on x509 parserAdam Borowski2022-07-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This code requires x509_load_certificate_list() to be built-in. Fixes: 60050ffe3d77 ("certs: Move load_certificate_list() to be with the asymmetric keys code") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Steven Rostedt <rostedt@goodmis.org> Link: https://lore.kernel.org/all/202206221515.DqpUuvbQ-lkp@intel.com/ Link: https://lore.kernel.org/all/20220712104554.408dbf42@gandalf.local.home/ Signed-off-by: Adam Borowski <kilobyte@angband.pl> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge tag 'perf_urgent_for_v5.19_rc8' of ↵Linus Torvalds2022-07-241-9/+10
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf fix from Borislav Petkov: - Reorganize the perf LBR init code so that a TSX quirk is applied early enough in order for the LBR MSR access to not #GP * tag 'perf_urgent_for_v5.19_rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/intel/lbr: Fix unchecked MSR access error on HSW
| * | perf/x86/intel/lbr: Fix unchecked MSR access error on HSWKan Liang2022-07-201-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fuzzer triggers the below trace. [ 7763.384369] unchecked MSR access error: WRMSR to 0x689 (tried to write 0x1fffffff8101349e) at rIP: 0xffffffff810704a4 (native_write_msr+0x4/0x20) [ 7763.397420] Call Trace: [ 7763.399881] <TASK> [ 7763.401994] intel_pmu_lbr_restore+0x9a/0x1f0 [ 7763.406363] intel_pmu_lbr_sched_task+0x91/0x1c0 [ 7763.410992] __perf_event_task_sched_in+0x1cd/0x240 On a machine with the LBR format LBR_FORMAT_EIP_FLAGS2, when the TSX is disabled, a TSX quirk is required to access LBR from registers. The lbr_from_signext_quirk_needed() is introduced to determine whether the TSX quirk should be applied. However, the lbr_from_signext_quirk_needed() is invoked before the intel_pmu_lbr_init(), which parses the LBR format information. Without the correct LBR format information, the TSX quirk never be applied. Move the lbr_from_signext_quirk_needed() into the intel_pmu_lbr_init(). Checking x86_pmu.lbr_has_tsx in the lbr_from_signext_quirk_needed() is not required anymore. Both LBR_FORMAT_EIP_FLAGS2 and LBR_FORMAT_INFO have LBR_TSX flag, but only the LBR_FORMAT_EIP_FLAGS2 requirs the quirk. Update the comments accordingly. Fixes: 1ac7fd8159a8 ("perf/x86/intel/lbr: Support LBR format V7") Reported-by: Vince Weaver <vincent.weaver@maine.edu> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20220714182630.342107-1-kan.liang@linux.intel.com
* | | Merge tag 'sched_urgent_for_v5.19_rc8' of ↵Linus Torvalds2022-07-241-1/+4
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull scheduler fix from Borislav Petkov: "A single fix to correct a wrong BUG_ON() condition for deboosted tasks" * tag 'sched_urgent_for_v5.19_rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: sched/deadline: Fix BUG_ON condition for deboosted tasks
| * | | sched/deadline: Fix BUG_ON condition for deboosted tasksJuri Lelli2022-07-211-1/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tasks the are being deboosted from SCHED_DEADLINE might enter enqueue_task_dl() one last time and hit an erroneous BUG_ON condition: since they are not boosted anymore, the if (is_dl_boosted()) branch is not taken, but the else if (!dl_prio) is and inside this one we BUG_ON(!is_dl_boosted), which is of course false (BUG_ON triggered) otherwise we had entered the if branch above. Long story short, the current condition doesn't make sense and always leads to triggering of a BUG. Fix this by only checking enqueue flags, properly: ENQUEUE_REPLENISH has to be present, but additional flags are not a problem. Fixes: 64be6f1f5f71 ("sched/deadline: Don't replenish from a !SCHED_DEADLINE entity") Signed-off-by: Juri Lelli <juri.lelli@redhat.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/20220714151908.533052-1-juri.lelli@redhat.com
* | | Merge tag 'x86_urgent_for_v5.19_rc8' of ↵Linus Torvalds2022-07-248-12/+36
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Borislav Petkov: "A couple more retbleed fallout fixes. It looks like their urgency is decreasing so it seems like we've managed to catch whatever snafus the limited -rc testing has exposed. Maybe we're getting ready... :) - Make retbleed mitigations 64-bit only (32-bit will need a bit more work if even needed, at all). - Prevent return thunks patching of the LKDTM modules as it is not needed there - Avoid writing the SPEC_CTRL MSR on every kernel entry on eIBRS parts - Enhance error output of apply_returns() when it fails to patch a return thunk - A sparse fix to the sev-guest module - Protect EFI fw calls by issuing an IBPB on AMD" * tag 'x86_urgent_for_v5.19_rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/speculation: Make all RETbleed mitigations 64-bit only lkdtm: Disable return thunks in rodata.c x86/bugs: Warn when "ibrs" mitigation is selected on Enhanced IBRS parts x86/alternative: Report missing return thunk details virt: sev-guest: Pass the appropriate argument type to iounmap() x86/amd: Use IBPB for firmware calls
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