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* Blackfin: cpufreq: fix typosMichael Hennerich2011-03-181-3/+3
| | | | | | | No functional changes here. Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: enable GENERIC_HARDIRQS_NO_DEPRECATEDThomas Gleixner2011-03-181-0/+1
| | | | | | | All chips converted. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SMP: convert to irq chip functionsMike Frysinger2011-03-181-1/+5
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: use accessor functions in show_interrupts()Thomas Gleixner2011-03-181-4/+6
| | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: use proper wrapper functions for modifying irq statusThomas Gleixner2011-03-184-4/+4
| | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: convert gpio irq_chip to new functionsThomas Gleixner2011-03-181-44/+48
| | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: convert mac irq_chip to new functionsThomas Gleixner2011-03-181-7/+11
| | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: convert error irq_chip to new functionsThomas Gleixner2011-03-181-7/+7
| | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: convert internal irq_chip to new functionsThomas Gleixner2011-03-181-13/+28
| | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: convert core irq_chip to new functionsThomas Gleixner2011-03-181-11/+11
| | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: use proper wrappers for irq_descThomas Gleixner2011-03-181-9/+5
| | | | | | | Fixup the open coded access to irq_desc and use the proper wrappers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: optimize startup codeMike Frysinger2011-03-181-69/+41
| | | | | | | Take advantage of more Blackfin-specific insns, and only initialize registers required by the ABI. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SMP: work around anomaly 05000491Sonic Zhang2011-03-188-12/+74
| | | | | | | | | | | | | | | | In order to safely work around anomaly 05000491, we have to execute IFLUSH from L1 instruction sram. The trouble with multi-core systems is that all L1 sram is visible only to the active core. So we can't just place the functions into L1 and call it directly. We need to setup a jump table and place the entry point in external memory. This will call the right func based on the active core. In the process, convert from the manual relocation of a small bit of code into Core B's L1 to the more general framework we already have in place for loading arbitrary pieces of code into L1. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SMP: implement cpu_freq supportGraf Yang2011-03-186-34/+70
| | | | | | | Re-use some of the existing cpu hotplugging code in the process. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: split optimization settings moreMike Frysinger2011-03-183-15/+47
| | | | | | | | | | | We need to place icache flush funcs into L1 inst sram to work around a hardware anomaly. But this currently breaks SMP support as the L1 inst sram is per-core and cannot be called directly. So in preparation for making that work, split the two options. Further, split out the SMP depend so that we can allow some for SMP. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SMP: disable preempt with smp_processor_id to send messagesSonic Zhang2011-03-181-6/+8
| | | | | | | | The smp_processor_id() API requires that preempt be disabled when calling it, so make sure it is when we go to send messages to other processors. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SMP: delay enabling caches until CPU is initializedsteven miao2011-03-181-2/+2
| | | | | | | | Defer bfin_setup_caches(cpu) to avoid unexpected faults due to the cpu state not yet being fully initialized. Signed-off-by: steven miao <realmz6@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SMP: use standard cache functionsMike Frysinger2011-03-181-3/+3
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SMP: PERCPU section should be PAGE alignedsteven miao2011-03-181-1/+1
| | | | | | | | Common code checks the alignment of some of the variables and calls BUG() if they aren't page aligned. Signed-off-by: steven miao <realmz6@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: ADI boards: enable pseudo debug insns supportMike Frysinger2011-03-1811-0/+11
| | | | | | | We use these insns when testing, so enable them by default for all of our development boards. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: kgdb: drop dead KGDB_THR_PROC_SWAP for SMP systemsSonic Zhang2011-03-181-4/+0
| | | | | | | Common code no longer defines this, so stop using it. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: dnp5370: drop MMC card detect supportAndreas Schallenberg2011-03-181-20/+0
| | | | | | | | The board doesn't actually have a pin hooked up to do card detection, so punt the code for it. Signed-off-by: Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add bfin_write_{or,and} helpersMike Frysinger2011-03-181-2/+14
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf548-ezkit: add CAN1 supportAaron Wu2011-03-181-7/+48
| | | | | Signed-off-by: Aaron Wu <aaronwu06@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: bf54x: add kconfig for UART2/3 DMA channel assignmentssteven miao2011-03-184-21/+102
| | | | | | | | | | The BF54x lacks dedicated DMA channels for the UART peripherals and need to be muxed between others. So add a kconfig option so people can select which channels the UARTs will use so they can pick between SPORTs and the less commonly used EPPI/PIXC peripherals. Signed-off-by: steven miao <realmz6@gmail.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: SMP: avoid section mismatch warningsSonic Zhang2011-03-181-1/+1
| | | | | | | | Since coreb_trampoline_start() calls coreb_start(), they need to be in the same section. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tileLinus Torvalds2011-03-1758-1007/+1648
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: (27 commits) arch/tile: support newer binutils assembler shift semantics arch/tile: fix deadlock bugs in rwlock implementation drivers/edac: provide support for tile architecture tile on-chip network driver: sync up with latest fixes arch/tile: support 4KB page size as well as 64KB arch/tile: add some more VMSPLIT options and use consistent naming arch/tile: fix some comments and whitespace arch/tile: export some additional module symbols arch/tile: enhance existing finv_buffer_remote() routine arch/tile: fix two bugs in the backtracer code arch/tile: use extended assembly to inline __mb_incoherent() arch/tile: use a cleaner technique to enable interrupt for cpu_idle() arch/tile: sync up with <arch/sim.h> and <arch/sim_def.h> changes arch/tile: fix reversed test of strict_strtol() return value arch/tile: avoid a simulator warning during bootup arch/tile: export <asm/hardwall.h> to userspace arch/tile: warn and retry if an IPI is not accepted by the target cpu arch/tile: stop disabling INTCTRL_1 interrupts during hypervisor downcalls arch/tile: fix __ndelay etc to work better arch/tile: bug fix: exec'ed task thought it was still single-stepping ... Fix up trivial conflict in arch/tile/kernel/vmlinux.lds.S (percpu alignment vs section naming convention fix)
| * arch/tile: support newer binutils assembler shift semanticsChris Metcalf2011-03-173-9/+29
| | | | | | | | | | | | | | | | This change supports building the kernel with newer binutils where a shift of greater than the word size is no longer interpreted silently as modulo the word size, but instead generates a warning. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * Merge tag 'v2.6.38' of ↵Chris Metcalf2011-03-17545-2464/+4801
| |\ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into for-linus
| * | arch/tile: fix deadlock bugs in rwlock implementationChris Metcalf2011-03-102-141/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first issue fixed in this patch is that pending rwlock write locks could lock out new readers; this could cause a deadlock if a read lock was held on cpu 1, a write lock was then attempted on cpu 2 and was pending, and cpu 1 was interrupted and attempted to re-acquire a read lock. The write lock code was modified to not lock out new readers. The second issue fixed is that there was a narrow race window where a tns instruction had been issued (setting the lock value to "1") and the store instruction to reset the lock value correctly had not yet been issued. In this case, if an interrupt occurred and the same cpu then tried to manipulate the lock, it would find the lock value set to "1" and spin forever, assuming some other cpu was partway through updating it. The fix is to enforce an interrupt critical section around the tns/store pair. In addition, this change now arranges to always validate that after a readlock we have not wrapped around the count of readers, which is only eight bits. Since these changes make the rwlock "fast path" code heavier weight, I decided to move all the rwlock code all out of line, leaving only the conventional spinlock code with fastpath inlines. Since the read_lock and read_trylock implementations ended up very similar, I just expressed read_lock in terms of read_trylock. As part of this change I also eliminate support for the now-obsolete tns_atomic mode. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | drivers/edac: provide support for tile architectureChris Metcalf2011-03-107-2/+384
| | | | | | | | | | | | | | | | | | | | | | | | Add tile support for the EDAC driver, which provides unified system error (memory, PCI, etc.) reporting. For now, the TILEPro port reports memory correctable error (CE) only. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | tile on-chip network driver: sync up with latest fixesChris Metcalf2011-03-101-446/+515
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Combine the "command" and "completion" locks into a single lock, on each egress queue, to improve efficiency. Support the use of 4KB pages in the "egress queue". Delete the unused "duplicate ACK compression" code. Filter "bad" (i.e. truncated) packets. Avoid corrupting "dev->napi_list", by sequentializing modifications. Deregister for incoming packets during stop, to reduce unexpected interrupts. Also, encourage active NAPI loops to complete before we disable NAPI, which would otherwise crash. Free any pending completions after shutting down LEPP. Use a single, permanently registered, IRQ handler, to avoid situations in which the IRQ handler was firing after being freed, and ignore any "unexpected" interrupts. Drop egress packets, instead of spinning, if the hardware cannot keep up, or is disconnected. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: support 4KB page size as well as 64KBChris Metcalf2011-03-1018-135/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tilera architecture traditionally supports 64KB page sizes to improve TLB utilization and improve performance when the hardware is being used primarily to run a single application. For more generic server scenarios, it can be beneficial to run with 4KB page sizes, so this commit allows that to be specified (by modifying the arch/tile/include/hv/pagesize.h header). As part of this change, we also re-worked the PTE management slightly so that PTE writes all go through a __set_pte() function where we can do some additional validation. The set_pte_order() function was eliminated since the "order" argument wasn't being used. One bug uncovered was in the PCI DMA code, which wasn't properly flushing the specified range. This was benign with 64KB pages, but with 4KB pages we were getting some larger flushes wrong. The per-cpu memory reservation code also needed updating to conform with the newer percpu stuff; before it always chose 64KB, and that was always correct, but with 4KB granularity we now have to pay closer attention and reserve the amount of memory that will be requested when the percpu code starts allocating. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: add some more VMSPLIT options and use consistent namingChris Metcalf2011-03-101-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This renames 3G_OPT to 2_75G, and adds 2_5G and 2_25G. For memory-intensive applications that are also network-buffer intensive it can be helpful to be able to tune the virtual address of the start of kernel memory. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: fix some comments and whitespaceChris Metcalf2011-03-107-24/+15
| | | | | | | | | | | | | | | | | | | | | | | | This is a grab bag of changes with no actual change to generated code. This includes whitespace and comment typos, plus a couple of stale comments being removed. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: export some additional module symbolsChris Metcalf2011-03-012-0/+8
| | | | | | | | | | | | | | | | | | | | | This adds a grab bag of symbols that have been missing for various modules. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: enhance existing finv_buffer_remote() routineChris Metcalf2011-03-014-56/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It now takes an additional argument so it can be used to flush-and-invalidate pages that are cached using hash-for-home as well those that are cached with coherence point on a single cpu. This allows it to be used more widely for changing the coherence point of arbitrary pages when necessary. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: fix two bugs in the backtracer codeChris Metcalf2011-03-011-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The first is that we were using an incorrect hand-rolled variant of __kernel_text_address() which didn't handle module PCs. We now just use the standard API. The second was that we weren't accounting for the three-level page table when we were trying to pre-verify the addresses on the 64-bit TILE-Gx processor; we now do that correctly. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: use extended assembly to inline __mb_incoherent()Chris Metcalf2011-03-014-41/+20
| | | | | | | | | | | | | | | | | | | | | This avoids having to maintain an additional separate assembly file, and of course the inline is slightly more efficient as well. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: use a cleaner technique to enable interrupt for cpu_idle()Chris Metcalf2011-03-011-11/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we used iret to atomically return to kernel PL with interrupts enabled. However, it turns out that we are architecturally guaranteed that we can just set and clear the "interrupt critical section" and only interrupt on the following instruction, so we now do that instead, since it's cleaner. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: sync up with <arch/sim.h> and <arch/sim_def.h> changesChris Metcalf2011-03-012-12/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | These headers are used by Linux but are maintained upstream. This change incorporates a few minor fixes to these headers, including a new sim_print() function, cleaner support for the sim_syscall() API, and a sim_query_cpu_speed() method. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: fix reversed test of strict_strtol() return valueChris Metcalf2011-03-011-1/+1
| | | | | | | | | | | | | | | | | | This fixes the "initfree" boot argument. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: avoid a simulator warning during bootupChris Metcalf2011-03-011-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | As the added comment says, we can sometimes see a coherence warning from our simulator if the "swapper_pgprot" variable on the boot cpu has not been evicted from cache by the time the other cpus come up. Force it to be evicted so we never see the warning. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: export <asm/hardwall.h> to userspaceChris Metcalf2011-03-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This should have been as part of the initial hardwall submission to LKML but was overlooked. The header provides the ioctl definitions for manipulating the hardwall fd, so needs to be available to userspace. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: warn and retry if an IPI is not accepted by the target cpuChris Metcalf2011-03-011-14/+19
| | | | | | | | | | | | | | | | | | | | | Previously we assumed this was impossible, but in fact it can happen. Handle it gracefully by retrying after issuing a warning. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: stop disabling INTCTRL_1 interrupts during hypervisor downcallsChris Metcalf2011-03-011-49/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem was that this could lead to IPIs being disabled during the softirq processing after a hypervisor downcall (e.g. for I/O), since both IPI and device interrupts use the INCTRL_1 downcall mechanism. When this happened at the wrong time, it could lead to deadlock. Luckily, we were already maintaining the per-interrupt state we need, and using it in the proper way in the hypervisor, so all we had to do was to change Linux to stop blocking downcall interrupts for the entire length of the downcall. (Now they're blocked while we're executing the downcall routine itself, but not while we're executing any subsequent softirq routines.) The hypervisor is doing a very small amount of work it no longer needs to do (masking INTCTRL_1 on entry to the client interrupt routine), but doing so means that older versions of Tile Linux will continue to work with a current hypervisor, so that seems reasonable. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: fix __ndelay etc to work betterChris Metcalf2011-03-015-11/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementations of __ndelay and __udelay call a hypervisor service to delay, but the hypervisor service isn't actually implemented very well, and the consensus is that Linux should handle figuring this out natively and not use a hypervisor service. By converting nanoseconds to cycles, and then spinning until the cycle counter reaches the desired cycle, we get several benefits: first, we are sensitive to the actual clock speed; second, we use less power by issuing a slow SPR read once every six cycles while we delay; and third, we properly handle the case of an interrupt by exiting at the target time rather than after some number of cycles. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: bug fix: exec'ed task thought it was still single-steppingChris Metcalf2011-03-013-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To handle single-step, tile mmap's a page of memory in the process space for each thread and uses it to construct a version of the instruction that we want to single step. If the process exec's, though, we lose that mapping, and the kernel needs to be aware that it will need to recreate it if the exec'ed process than tries to single-step as well. Also correct some int32_t to s32 for better kernel style. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: catch up with section naming convention in 2.6.35Chris Metcalf2011-03-015-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The convention changed to, e.g., ".data..page_aligned". This commit fixes the places in the tile architecture that were still using the old convention. One tile-specific section (.init.page) was dropped in favor of just using an "aligned" attribute. Sam Ravnborg <sam@ravnborg.org> pointed out __PAGE_ALIGNED_BSS, etc. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
| * | arch/tile: Fix atomic_read() definition to use ACCESS_ONCEChris Metcalf2011-02-251-1/+1
| | | | | | | | | | | | | | | | | | | | | This adds the volatile cast which forces the compiler to emit the load. Suggested by Peter Zijlstra <peterz@infradead.org>. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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