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* clk: Convert __clk_get_flags() to clk_hw_get_flags()Stephen Boyd2015-08-2417-21/+21
| | | | | | | | | | | | | | | | | | | Mostly converted with the following snippet: @@ struct clk_hw *E; @@ -__clk_get_flags(E->clk) +clk_hw_get_flags(E) Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: Replace __clk_get_num_parents with clk_hw_get_num_parents()Stephen Boyd2015-08-2415-20/+20
| | | | | | | | | | | | | | | | | | | | | | | Mostly converted with the following semantic patch: @@ struct clk_hw *E; @@ -__clk_get_num_parents(E->clk) +clk_hw_get_num_parents(E) Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Chao Xie <chao.xie@marvell.com> Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: "Emilio López" <emilio@elopez.com.ar> Acked-by: Tero Kristo <t-kristo@ti.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: Add clk_hw_*() APIs for use by clk providersStephen Boyd2015-08-242-0/+70
| | | | | | | | clk providers shouldn't need to use the consumer APIs (clk.h). Add provider APIs to replace the __clk_*() APIs that take a struct clk_hw as their first argument instead of a struct clk. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: rockchip: Fix SPIF special clock definitionSjoerd Simons2015-08-121-3/+3
| | | | | | | | | | | | | Neither spdif_src nor spdif_pll exists, judging by the vendor kernel in both cases spdif_pre was meant. This brings the naming in line and hierachy in line with that of sclk_i2s0. Also allow sclk_spdif and spdif_frac to change their parents rate as that the upstream dividers are purely there to feed sclk_spdif Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: bcm2835: Drop the fixed sys_pclk.Eric Anholt2015-08-121-5/+0
| | | | | | | | | Nothing uses it, and I can't find any evidence that anything ever has. Its role is now filled by the core clock in the firmware driver. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* clk: track the orphan status of clocks and their childrenHeiko Stuebner2015-08-121-3/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While children of orphan clocks are not carried in the orphan-list itself, they're nevertheless orphans in their own right as they also don't have an input-rate available. To ease tracking if a clock is an orphan or has an orphan in its parent path introduce an orphan field into struct clk and update it and the fields in child-clocks when a clock gets added or removed from the orphan-list. Suggested-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Alex Elder <elder@linaro.org> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: kernel@pengutronix.de Cc: Zhangfei Gao <zhangfei.gao@linaro.org> Cc: Santosh Shilimkar <ssantosh@kernel.org> Cc: Chao Xie <chao.xie@marvell.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Robert Jarzmik <robert.jarzmik@free.fr> Cc: Georgi Djakov <georgi.djakov@linaro.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Barry Song <baohua@kernel.org> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Gabriel FERNANDEZ <gabriel.fernandez@st.com> Cc: emilio@elopez.com.ar Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Michal Simek <michal.simek@xilinx.com> [sboyd@codeaurora.org: s/clk/core/ in new function] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: sunxi: Add a simple gates driverMaxime Ripard2015-08-123-177/+159
| | | | | | | | | | | | | | | The gates were handled with a common piece of framework that was registering all gates array, that was not using the CLK_OF_DECLARE logic, and was not using clock-indices but some private masks that were pretty much equivalent. Move this code in a new driver that handles all the gates array and solves both these issues. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> [sboyd@codeaurora.org: Include clk.h for consumer API usage] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* ARM: sun9i: Wrap the clock-indicesMaxime Ripard2015-08-121-10/+22
| | | | | | | | Wrap the clock-indices to match the wrapping of the clock-output-names in order to make it easier to match indices to names. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* ARM: sun8i: Add clock indicesMaxime Ripard2015-08-121-0/+15
| | | | | | | | The A23 and A33 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* ARM: sun7i: Add clock indicesMaxime Ripard2015-08-121-0/+23
| | | | | | | | The A20 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* ARM: sun6i: Add clock indicesMaxime Ripard2015-08-121-0/+24
| | | | | | | | The A31 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* ARM: sun5i: Add clock indicesMaxime Ripard2015-08-123-3/+39
| | | | | | | | The A10s and A13 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* ARM: sun4i: Add clock indicesMaxime Ripard2015-08-121-17/+52
| | | | | | | | The A10 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* Merge tag 'imx-clk-4.3' of ↵Michael Turquette2015-08-126-2/+684
|\ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next The i.MX clock updates for 4.3: - Provide a better IPU clock initial settings on imx6dl for getting HDMI and LVDS at the same time. - Add clock driver support for i.MX6UL SoC - Add a second clock for RTC device on i.MX31 and i.MX35
| * clk: imx35: define two clocks for rtcPhilippe Reynes2015-08-051-1/+5
| | | | | | | | | | | | | | | | | | The imx35 don't define clocks for rtc. This patch add two clocks, as needed by the mxc rtc driver. Signed-off-by: Philippe Reynes <tremyfr@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx31: add a second rtc clockPhilippe Reynes2015-08-051-1/+2
| | | | | | | | | | | | | | | | | | The mxc rtc driver needs two clock. It was defined only one clock, so we define the second clock. Signed-off-by: Philippe Reynes <tremyfr@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: add imx6ul clk tree supportFrank Li2015-07-143-0/+673
| | | | | | | | | | | | | | | | | | | | Add imx6ul clock driver support. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Bai Ping <b51503@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * clk: imx: clk-imx6q: Provide initial IPU clock settings for mx6dlFabio Estevam2015-07-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently it is not possible to use HDMI and LVDS at the same time on a imx6dl-sabresd board. Fix this usecase by setting IMX6QDL_CLK_PLL3_PFD1_540M to 540MHz and also by setting it as the parent of IMX6QDL_CLK_IPU1_SEL. Based on the configuration done in the FSL kernel. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | clk/mmp: use kmemdup rather than duplicating its implementationAndrzej Hajda2015-08-071-4/+3
| | | | | | | | | | | | | | | | | | | | The patch was generated using fixed coccinelle semantic patch scripts/coccinelle/api/memdup.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2014320 Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: hisi: refine parameter checking for initLeo Yan2015-08-031-8/+3
| | | | | | | | | | | | | | | | | | | | *of_iomap()* will check the device node pointer, and if the pointer is NULL it will return error code. So refine clock's init flow by checking the device node with this simple way; and polish a little for the print out message. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: versatile: off by one in clk_sp810_timerclken_of_get()Dan Carpenter2015-07-291-2/+2
| | | | | | | | | | | | | | | | | | The ">" should be ">=" or we end up reading beyond the end of the array. Fixes: 6e973d2c4385 ('clk: vexpress: Add separate SP810 driver') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: exynos4: Fix wrong clock for Exynos4x12 ADCKrzysztof Kozlowski2015-07-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver. However TSADC is present only on Exynos4210 so on Trats2 board (with Exynos4412 SoC) the exynos-adc driver could not be probed: ERROR: could not get clock /adc@126C0000:adc(0) exynos-adc 126c0000.adc: failed getting clock, err = -2 exynos-adc: probe of 126c0000.adc failed with error -2 Instead on Exynos4x12 SoCs the main clock used by Analog to Digital Converter is located in different register and it is named in datasheet as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock is the same as purpose of TSADC from Exynos4210. The patch adds gate clock for Exynos4x12 using the proper register so backward compatibility is preserved. This fixes the probe of exynos-adc driver on Exynos4x12 boards and allows accessing sensors connected to it on Trats2 board (ntc,ncp15wb473 AP and battery thermistors). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: <stable@vger.kernel.org> Fixes: c63c57433003 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12") Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: kill off set_irq_flags usageRob Herring2015-07-281-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set_irq_flags is ARM specific with custom flags which have genirq equivalents. Convert drivers to use the genirq interfaces directly, so we can kill off set_irq_flags. The translation of flags is as follows: IRQF_VALID -> !IRQ_NOREQUEST IRQF_PROBE -> !IRQ_NOPROBE IRQF_NOAUTOEN -> IRQ_NOAUTOEN For IRQs managed by an irqdomain, the irqdomain core code handles clearing and setting IRQ_NOREQUEST already, so there is no need to do this in .map() functions and we can simply remove the set_irq_flags calls. Some users also modify IRQ_NOPROBE and this has been maintained although it is not clear that is really needed. There appears to be a great deal of blind copy and paste of this code. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Mike Turquette <mturquette@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: zx: Constify parent names in clock init dataJun Nie2015-07-281-20/+20
| | | | | | | | | | | | | | | | The array of parent names can be made as array of const pointers to const strings. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: zx: Add audio and GPIO clock for zx296702Jun Nie2015-07-282-4/+105
| | | | | | | | | | | | | | Add SPDIF/I2S and GPIO clock for zx296702 Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: zx: Add audio div clock method for zx296702Jun Nie2015-07-283-3/+149
| | | | | | | | | | | | | | Add SPDIF/I2S divider clock method for zx296702 Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: s2mps11: Use kcalloc instead of kzalloc for array allocationVaibhav Hiremath2015-07-281-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up the driver for, - Use devm_kcalloc() variant instead of devm_kzalloc() for array allocation. - clk_prepare()/unprepare(), remove "ret" variable as it is not required - use __exit for cleanup function As I am referring this driver as a reference for my 88pm800 clk driver, applying same changes here as well. Signed-off-by: Vaibhav Hiremath <vaibhav.hiremath@linaro.org> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: Silence warnings about lock imbalancesStephen Boyd2015-07-281-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | The recursive spinlock implementation trips up sparse and it complains that these functions have lock imbalances. That isn't really true though, so add some __acquires() and __releases() information so that sparse is quiet. drivers/clk/clk.c:116:22: warning: context imbalance in 'clk_enable_lock' - wrong count at exit drivers/clk/clk.c:141:9: warning: context imbalance in 'clk_enable_unlock' - unexpected unlock Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: basic-type: Silence warnings about lock imbalancesStephen Boyd2015-07-284-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The basic clock types use conditional locking for the register accessor spinlocks. Add __acquire() and __release() markings in the right locations so that sparse isn't tripped up on the conditional locking. drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: qcom: Give clk-qcom.ko module a GPLv2 licenseStephen Boyd2015-07-281-0/+3
| | | | | | | | | | | | | | The missing license causes the clk-qcom.ko module to taint the kernel. Add the appropriate license to avoid taint. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: gpio: Mark parent_names array constStephen Boyd2015-07-282-7/+8
| | | | | | | | | | | | | | | | Let's encourage const arrays of parent names like other basic clock types. Cc: Sergej Sawazki <ce3a@gmx.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge branch 'v4.3-topic/clk-samsung' of ↵Michael Turquette2015-07-284-2/+63
|\ \ | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into clk-next
| * | clk: exynos3250: Add cpu clock configuration data and instaniate cpu clockChanwoo Choi2015-07-242-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add CPU clock configuration data and instantiate the CPU clock type for Exynos3250 to support Samsung specific cpu-clock type. Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
| * | clk: exynos5250: add cpu clock configuration data and instantiate cpu clockThomas Abraham2015-07-242-0/+32
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos5250. Cc: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [b.zolnierkie: split exynos5250 support from the original patch] [b.zolnierkie: moved E5250_CPU_DIV[0,1] macros to clk-exynos5250.c] Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org> Tested-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
* | clk: allow a clk divider with max divisor when zeroJim Quinlan2015-07-282-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows certain Broadcom STB clock dividers to be used with clk-divider.c. It allows for a clock whose field value is the equal to the divisor, execpt when the field value is zero, in which case the divisor is 2^width. For example, consider a divisor clock with a two bit field: value divisor 0 4 1 1 2 2 3 3 Signed-off-by: Jim Quinlan <jim2101024@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* | clk: socfpga: switch to GENMASK()Andy Shevchenko2015-07-285-5/+4
| | | | | | | | | | | | | | | | Convert the code to use GENMASK() helper instead of div_mask() macro. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: pxa: fix core frequency reporting unitRobert Jarzmik2015-07-283-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Legacy drivers which are not yet ported, such as cpufreq-pxa[23]xx, rely on pxaXXx_get_clk_frequency_khz() to find the CPU core frequency. This reporting was broken because the expected unit is kHz and not Hz. Fix the reporting for pxa25x, pxa27x and pxa3xx. Fixes: fe7710fae477 ("clk: add pxa25x clock drivers") Fixes: d40670dc6169 ("clk: add pxa27x clock drivers") Fixes: 9bbb8a338fb2 ("clk: pxa: add pxa3xx clock driver") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | clk: rockchip: Fix PLL bandwidthDouglas Anderson2015-07-284-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the TRM we see that BWADJ is "a 12-bit bus that selects the values 1-4096 for the bandwidth divider (NB)": NB = BWADJ[11:0] + 1 The recommended setting of NB: NB = NF / 2. So: NB = NF / 2 BWADJ[11:0] + 1 = NF / 2 BWADJ[11:0] = NF / 2 - 1 Right now, we have: { \ .rate = _rate##U, \ .nr = _nr, \ .nf = _nf, \ .no = _no, \ .bwadj = (_nf >> 1), \ } That means we set bwadj to NF / 2, not NF / 2 - 1 All of this is a bit confusing because we specify "NR" (the 1-based value), "NF" (the 1-based value), "NO" (the 1-based value), but "BWADJ" (the 0-based value) instead of "NB" (the 1-based value). Let's change to working with "NB" and fix the off by one error. This may affect PLL jitter in a small way (hopefully for the better). Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge branch 'cleanup-clk-h-includes' into clk-nextStephen Boyd2015-07-28165-147/+112
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * cleanup-clk-h-includes: (62 commits) clk: Remove clk.h from clk-provider.h clk: h8300: Remove clk.h and clkdev.h includes clk: at91: Include clk.h and slab.h clk: ti: Switch clk-provider.h include to clk.h clk: pistachio: Include clk.h clk: ingenic: Include clk.h clk: si570: Include clk.h clk: moxart: Include clk.h clk: cdce925: Include clk.h clk: Include clk.h in clk.c clk: zynq: Include clk.h clk: ti: Include clk.h clk: sunxi: Include clk.h and remove unused clkdev.h includes clk: st: Include clk.h clk: qcom: Include clk.h clk: highbank: Include clk.h clk: bcm: Include clk.h clk: versatile: Remove clk.h and clkdev.h includes clk: ux500: Remove clk.h and clkdev.h includes clk: tegra: Properly include clk.h ...
| * | clk: Remove clk.h from clk-provider.hStephen Boyd2015-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove clk.h from clk-provider.h so that we can clearly split clk providers from clk consumers. This will allow us to quickly detect when clock providers are using the consumer APIs by looking at the includes. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: h8300: Remove clk.h and clkdev.h includesStephen Boyd2015-07-202-4/+0
| | | | | | | | | | | | | | | | | | | | | Neither of these includes are used in these files, remove them. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: at91: Include clk.h and slab.hStephen Boyd2015-07-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This clock provider uses the consumer API, so include clk.h explicitly. Also include slab.h instead of relying on clkdev.h for it. Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: ti: Switch clk-provider.h include to clk.hStephen Boyd2015-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This file isn't a clock provider but uses the consumer API, so include clk.h instead of clk-provider.h. Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: pistachio: Include clk.hStephen Boyd2015-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This clock provider uses the consumer API, so include clk.h explicitly. Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: ingenic: Include clk.hStephen Boyd2015-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This clock provider uses the consumer API, so include clk.h explicitly. Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paul Cercueil <paul@crapouillou.net> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: si570: Include clk.hStephen Boyd2015-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This clock provider uses the consumer API, so include clk.h explicitly. Cc: Guenter Roeck <linux@roeck-us.net> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: moxart: Include clk.hStephen Boyd2015-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This clock provider uses the consumer API, so include clk.h explicitly. Cc: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: cdce925: Include clk.hStephen Boyd2015-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This clock provider uses the consumer API, so include clk.h explicitly. Cc: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: Include clk.h in clk.cStephen Boyd2015-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This file implements the clk API and so it should include clk.h directly instead of indirectly including it through clk-provider.h. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| * | clk: zynq: Include clk.hStephen Boyd2015-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This clock provider uses the consumer API, so include clk.h explicitly. Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-20 12:13:24 +0000