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* clk: qcom: dispcc-sc7180: switch to parent_hwsDmitry Baryshkov2023-01-101-4/+4
| | | | | | | | | Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103145515.1164020-3-dmitry.baryshkov@linaro.org
* clk: qcom: dispcc-sm8450: switch to parent_hwsDmitry Baryshkov2023-01-101-106/+106
| | | | | | | | | Change several entries of parent_data to use parent_hws instead, which results in slightly more ovbious code. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103145515.1164020-2-dmitry.baryshkov@linaro.org
* Merge branch '20230104093450.3150578-2-abel.vesa@linaro.org' into clk-for-6.3Bjorn Andersson2023-01-100-0/+0
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| * dt-bindings: clock: Add SM8550 TCSR CC clocksAbel Vesa2023-01-102-0/+73
| | | | | | | | | | | | | | | | | | Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-2-abel.vesa@linaro.org
* | clk: qcom: add SM8550 DISPCC driverNeil Armstrong2023-01-103-0/+1817
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the display clock controller found in SM8550 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based on the SM8450 support. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-3-8a03d348c572@linaro.org
* | clk: qcom: clk-alpha-pll: define alias of LUCID OLE reset ops to EVO reset opsNeil Armstrong2023-01-101-0/+1
| | | | | | | | | | | | | | | | | | | | Add an alias of LUCID OLE reset ops to EVO reset ops similar to other aliases. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-2-8a03d348c572@linaro.org
* | dt-bindings: clock: document SM8550 DISPCC clock controllerNeil Armstrong2023-01-102-0/+206
| | | | | | | | | | | | | | | | | | | | Document device tree bindings for display clock controller for Qualcomm SM8550 SoC. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org
* | Merge tag '1672656511-1931-1-git-send-email-quic_akhilpo@quicinc.com' into ↵Bjorn Andersson2023-01-103-5/+37
|\ \ | | | | | | | | | | | | | | | clk-for-6.3 v6.2-rc1 + 1672656511-1931-1-git-send-email-quic_akhilpo@quicinc.com
| * | clk: qcom: gdsc: Support 'synced_poweroff' genpd flagAkhil P Oommen2023-01-101-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the newly added 'synced_poweroff' genpd flag. This allows some clients (like adreno gpu driver) to request gdsc driver to ensure a votable gdsc (like gpucc cx gdsc) has collapsed at hardware. Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102161757.v5.2.Ic128c1df50b7fc9a6b919932a3b41a799b5ed5e8@changeid
| * | PM: domains: Allow a genpd consumer to require a synced power offUlf Hansson2023-01-102-0/+31
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some genpd providers doesn't ensure that it has turned off at hardware. This is fine until the consumer really requires during some special scenarios that the power domain collapse at hardware before it is turned ON again. An example is the reset sequence of Adreno GPU which requires that the 'gpucc cx gdsc' power domain should move to OFF state in hardware at least once before turning in ON again to clear the internal state. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102161757.v5.1.I3e6b1f078ad0f1ca9358c573daa7b70ec132cdbe@changeid
* | clk: qcom: sdm845: Use generic clk_sync_state_disable_unused callbackAbel Vesa2023-01-104-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By adding the newly added clk_sync_state_disable_unused as sync_state callback to all sdm845 clock providers, we make sure that no clock belonging to these providers gets disabled on clk_disable_unused, but rather they are disabled on sync_state, when it is safe, since all the consumers build as modules have had their chance of enabling their own clocks. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221227204528.1899863-2-abel.vesa@linaro.org
* | clk: Add generic sync_state callback for disabling unused clocksAbel Vesa2023-01-102-11/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are unused clocks that need to remain untouched by clk_disable_unused, and most likely could be disabled later on sync_state. So provide a generic sync_state callback for the clock providers that register such clocks. Then, use the same mechanism as clk_disable_unused from that generic callback, but pass the device to make sure only the clocks belonging to the current clock provider get disabled, if unused. Also, during the default clk_disable_unused, if the driver that registered the clock has the generic clk_sync_state_disable_unused callback set for sync_state, skip disabling its clocks. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221227204528.1899863-1-abel.vesa@linaro.org
* | clk: qcom: rpmh: add clocks for sa8775pBartosz Golaszewski2023-01-101-0/+17
| | | | | | | | | | | | | | | | | | Extend the driver with a description of clocks for sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109174511.1740856-6-brgl@bgdev.pl
* | dt-bindings: clock: qcom-rpmhcc: document the clock for sa8775pBartosz Golaszewski2023-01-101-0/+1
| | | | | | | | | | | | | | | | | | Add a new compatible for SA8775P platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109174511.1740856-5-brgl@bgdev.pl
* | clk: qcom: krait-cc: fix wrong pointer passed to IS_ERR()Yang Yingliang2023-01-101-2/+2
| | | | | | | | | | | | | | | | | | It should be 'mux' passed to IS_ERR/PTR_ERR(). Fixes: 56a655e1c41a ("clk: qcom: krait-cc: convert to parent_data API") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104080235.1748953-1-yangyingliang@huawei.com
* | clk: qcom: Add TCSR clock driver for SM8550Abel Vesa2023-01-063-0/+200
| | | | | | | | | | | | | | | | | | | | | | | | The TCSR clock controller found on SM8550 provides refclks for PCIE, USB and UFS. Add clock driver for it. This patch is based on initial code downstream. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-5-abel.vesa@linaro.org
* | clk: qcom: rpmh: Add support for SM8550 rpmh clocksAbel Vesa2023-01-061-0/+36
| | | | | | | | | | | | | | | | | | Adds the RPMH clocks present in SM8550 SoC. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-4-abel.vesa@linaro.org
* | dt-bindings: clock: Add RPMHCC for SM8550Abel Vesa2023-01-061-0/+1
| | | | | | | | | | | | | | | | | | Add bindings and update documentation for clock rpmh driver on SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-3-abel.vesa@linaro.org
* | dt-bindings: clock: Add SM8550 TCSR CC clocksAbel Vesa2023-01-062-0/+73
| | | | | | | | | | | | | | | | | | Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-2-abel.vesa@linaro.org
* | dt-bindings: clock: qcom,gcc-sc8280xp: document power domainKrzysztof Kozlowski2023-01-021-0/+7
| | | | | | | | | | | | | | | | | | | | GCC clock controller is supplied by CX power domain: sc8280xp-crd.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected) Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230102085909.24620-1-krzysztof.kozlowski@linaro.org
* | clk: qcom: dispcc-sm6125: Fix compatible string to match bindingsMarijn Suijten2022-12-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to generic rules the SoC name should be first: arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: clock-controller@5f00000: compatible: 'oneOf' conditional failed, one must be fixed: 'qcom,dispcc-sm6125' does not match '^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$' And this is already reflected by the bindings submitted prior to the addition of this driver. Any DTS following these rules will end up with a non-probing driver because of this mismatch. Fixes: 6e87c8f07407 ("clk: qcom: Add display clock controller driver for SM6125") Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221222210140.278077-1-marijn.suijten@somainline.org
* | clk: qcom: Add camera clock controller driver for SM6350Konrad Dybcio2022-12-283-0/+1914
| | | | | | | | | | | | | | | | | | Add support for the camera clock controller found on SM6350. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213152617.296426-2-konrad.dybcio@linaro.org
* | dt-bindings: clock: add QCOM SM6350 camera clock bindingsKonrad Dybcio2022-12-282-0/+158
| | | | | | | | | | | | | | | | | | | | | | Add device tree bindings for camera clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213152617.296426-1-konrad.dybcio@linaro.org
* | clk: qcom: smd-rpm: remove usage of platform nameDmitry Baryshkov2022-12-281-665/+663
| | | | | | | | | | | | | | | | | | | | | | Now that all clocks have individual names, remove the names of SoCs from the SMD RPM clock definitions. Replace it with the common clk_smd_rpm_ prefix. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-20-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: rename SMD_RPM_BUS clocksDmitry Baryshkov2022-12-281-121/+131
| | | | | | | | | | | | | | | | | | | | | | | | Add special macro for the clocks of QCOM_SMD_RPM_BUS_CLK type. Use it to insert the _bus_N part into the clock symbol name. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-19-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: rename the qcm2290 rf_clk3 clocksDmitry Baryshkov2022-12-281-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | Rename the qcm2290_rf_clk3 clocks adding 38m4 prefix to distinguish it from the common (19.2 MHz) rf_clk3. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-18-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: rename SMD_RPM_BRANCH clock symbolsDmitry Baryshkov2022-12-281-48/+54
| | | | | | | | | | | | | | | | | | | | | | | | To ease distinguishing between branch and non-branch clocks (e.g. aggre1_noc, aggre2_noc and qdss) add '_branch' to all SMD_RPM_BRANCH* clocks. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-17-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: simplify SMD_RPM/_BRANCH/_QDSS clock definitionsDmitry Baryshkov2022-12-281-43/+53
| | | | | | | | | | | | | | | | | | | | | | | | Remove the duplication between the names of the normal and active-only clocks by moving common sufixes to the clock definition macros. This simplifies adding new clock definitions and reviewing existing defs. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-16-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: simplify XO_BUFFER clocks definitionsDmitry Baryshkov2022-12-281-29/+27
| | | | | | | | | | | | | | | | | | | | | | | | Remove the duplication between the names of the normal and active-only XO_BUFFER and XO_BUFFER_PINCTRL clocks by using preprocessor logic to add _a suffix. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-15-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: rename some msm8974 active-only clocksDmitry Baryshkov2022-12-281-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename msm8974_diff_a_clk, msm8974_div_a_clk1 and msm8974_div_a_clk2 to move the _a suffix to the end of the name. This follows the pattern used by other active-only clocks and thus makes it possible to simplify clock definitions. This changes the userspace-visible names for this clocks. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-14-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: move clock definitions togetherDmitry Baryshkov2022-12-281-69/+59
| | | | | | | | | | | | | | | | | | | | To ease review and reuse group all clock definitions together. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-13-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: fix alignment of line breaking backslashesDmitry Baryshkov2022-12-281-16/+16
| | | | | | | | | | | | | | | | | | | | | | The commit 52a436e0b7fe ("clk: qcom: smd-rpm: Switch to parent_data") introduced ragged right alignment for the line breaking backslash. Fix it to make the code look consistently. Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-12-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: drop the rpm_status_id fieldDmitry Baryshkov2022-12-281-13/+7
| | | | | | | | | | | | | | | | | | | | | | | | The rpm_status_id field is a leftover from the non-SMD clocks. It is of no use for the SMD-RPM clock driver and is always equal to zero. Drop it completely. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-11-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: add XO_BUFFER clock for each XO_BUFFER_PINCTRL clockDmitry Baryshkov2022-12-281-29/+18
| | | | | | | | | | | | | | | | | | | | | | | | For each XO_BUFFER_PINCTRL there is a corresponding XO_BUFFER clock. Add them automatically to drop the duplication between the clock definitions. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-10-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: remove duplication between sm6375 and sm6125 clocksDmitry Baryshkov2022-12-281-6/+4
| | | | | | | | | | | | | | | | | | | | Reuse sm6125's MMAXI clocks for sm6375. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-9-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: rename msm8992_ln_bb_* clocks to qcs404_ln_bb_*Dmitry Baryshkov2022-12-281-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For each of XO_BUFFER_PINCTRL clocks there is a corresponding XO_BUFFER clock with the similar name (e.g. msm8998_ln_bb_clk3_pin vs msm8998_ln_bb_clk3). For qcs404_ln_bb_clk_pin there is no qcs404_ln_bb_clk, since the msm8992_ln_bb_clk was used instead (even for qcs404 platform). Follow the usual practice and rename msm8992_ln_bb_clk clocks to qcs404_ln_bb_clk (and rename active-only clock in a similar way). This is a preparation step for the next patch, which will merge XO_BUFFER and XO_BUFFER_PINCTRL definitions. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-8-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: use msm8998_ln_bb_clk2 for qcm2290 SoCDmitry Baryshkov2022-12-281-3/+2
| | | | | | | | | | | | | | | | | | | | | | The qcm2290's ln_bb_clk2 is identical to the freshly added msm8998's ln_bb_clk2 one. Use the latter and drop the SoC-specific version. Reviewed-by: Alex Elder <elder@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-7-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: add missing ln_bb_clkN clocksDmitry Baryshkov2022-12-281-20/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer platforms (msm8998, sdm660, sm6125) have low noise LN_BB_CLKn clocks. The driver already uses proper clock indices (RPM_SMD_LN_BB_CLKn). Fix clock names used by these platforms. Fixes: a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries") Fixes: edeb2ca74716 ("clk: qcom: smd: Add support for SM6125 rpm clocks") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-6-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: remove duplication between qcs404 and qcm2290 clocksDmitry Baryshkov2022-12-281-7/+4
| | | | | | | | | | | | | | | | | | | | | | Reuse qcs404's QPIC and BIMC_GPU clock for qcm2290. Fixes: 78b727d02815 ("clk: qcom: smd-rpm: Add QCM2290 RPM clock support") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-5-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: remove duplication between MMXI and MMAXI definesDmitry Baryshkov2022-12-282-3/+2
| | | | | | | | | | | | | | | | | | | | | | The commit 644c42295592 ("clk: qcom: smd: Add SM6375 clocks") added a duplicate of the existing define QCOM_SMD_RPM_MMAXI_CLK, drop it now. Fixes: 644c42295592 ("clk: qcom: smd: Add SM6375 clocks") Reviewed-by: Alex Elder <elder@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-4-dmitry.baryshkov@linaro.org
* | clk: qcom: smd-rpm: enable pin-controlled ln_bb_clk clocks on qcs404Dmitry Baryshkov2022-12-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") defined the pin-controlled ln_bb_clk clocks, but didn't add them to the qcs404_clks array. Add them to make these clocks usable to platform devices. Fixes: eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") Reviewed-by: Alex Elder <elder@linaro.org? Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-3-dmitry.baryshkov@linaro.org
* | dt-bindings: clocks: qcom: rpmcc: add LN_BB_CLK_PIN clocksDmitry Baryshkov2022-12-281-0/+2
| | | | | | | | | | | | | | | | | | | | Add pin-controlled Low-Noise BB clock definition. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-2-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-sm6115: Use floor_ops for SDCC1/2 core clkKonrad Dybcio2022-12-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | Just like in case of other SoCs change SDCC1/SDCC2 ops to floor to avoid overclocking the controller. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Iskren Chernev <me@iskren.info> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209123910.178609-1-konrad.dybcio@linaro.org
* | clk: qcom: gcc-qcs404: add support for GDSCsDmitry Baryshkov2022-12-271-0/+24
| | | | | | | | | | | | | | | | | | Add support for two GDSCs provided by this clock controller. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-13-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-qcs404: sort out the cxo clockDmitry Baryshkov2022-12-271-56/+41
| | | | | | | | | | | | | | | | | | | | | | The GCC driver registers the cxo clock as a thin wrapper around board's xo_board clock. Nowadays we can use the xo_board directly in all the clocks that use it. Use the fw_name "cxo" for this clock. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-12-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_namesDmitry Baryshkov2022-12-271-249/+275
| | | | | | | | | | | | | | | | | | | | | | | | Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-11-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-qcs404: move PLL clocks upDmitry Baryshkov2022-12-271-149/+149
| | | | | | | | | | | | | | | | | | | | Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-10-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-qcs404: get rid of the test clockDmitry Baryshkov2022-12-271-34/+0
| | | | | | | | | | | | | | | | | | | | | | The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-9-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clockDmitry Baryshkov2022-12-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The QCS404 uses 28nm HDMI PHY. The in-kernel driver doesn't provide the PLL (yet), but the out of tree patches used the name "hdmi_pll" for it. Other Qualcomm HDMI PHYs use either the name "hdmi_pll" (8960) or "hdmipll" (8996). Thus change the expected HDMI PLL clock name to "hdmi_pll". Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-8-dmitry.baryshkov@linaro.org
* | clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parentsDmitry Baryshkov2022-12-271-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | The QCS404 uses 28nm LPM DSI PHY, which registers dsi0pll and dsi0pllbyte clocks. Fix all DSI PHY clock names used as parents inside the GCC driver. Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-7-dmitry.baryshkov@linaro.org
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