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* | | | powerpc/mm: Implement STRICT_KERNEL_RWX on PPC32Christophe Leroy2017-08-154-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements STRICT_KERNEL_RWX on PPC32. As for CONFIG_DEBUG_PAGEALLOC, it deactivates BAT and LTLB mappings in order to allow page protection setup at the level of each page. As BAT/LTLB mappings are deactivated, there might be a performance impact. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/mm: Fix kernel RAM protection after freeing unused memory on PPC32Christophe Leroy2017-08-152-4/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As seen below, allthough the init sections have been freed, the associated memory area is still marked as executable in the page tables. ~ dmesg [ 5.860093] Freeing unused kernel memory: 592K (c0570000 - c0604000) ~ cat /sys/kernel/debug/kernel_page_tables ---[ Start of kernel VM ]--- 0xc0000000-0xc0497fff 4704K rw X present dirty accessed shared 0xc0498000-0xc056ffff 864K rw present dirty accessed shared 0xc0570000-0xc059ffff 192K rw X present dirty accessed shared 0xc05a0000-0xc7ffffff 125312K rw present dirty accessed shared ---[ vmalloc() Area ]--- This patch fixes that. The implementation is done by reusing the change_page_attr() function implemented for CONFIG_DEBUG_PAGEALLOC Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/mm: Ensure change_page_attr() doesn't invalidate pinned TLBsChristophe Leroy2017-08-151-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | __change_page_attr() uses flush_tlb_page(). flush_tlb_page() uses tlbie instruction, which also invalidates pinned TLBs, which is not what we expect. This patch modifies the implementation to use flush_tlb_kernel_range() instead. This will make use of tlbia which will preserve pinned TLBs. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Reduce DTLB miss handler by one insnChristophe Leroy2017-08-151-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reduces the DTLB miss handler hot path (user address path) by one instruction by preserving r10. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: mark init functions with __initChristophe Leroy2017-08-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | setup_initial_memory_limit() is only called during init. mmu_patch_cmp_limit() is only called from 8xx_mmu.c Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Do not allow Pinned TLBs with STRICT_KERNEL_RWX or DEBUG_PAGEALLOCChristophe Leroy2017-08-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pinning TLBs bypasses STRICT_KERNEL_RWX or DEBUG_PAGEALLOC protections so it should only be allowed when those are not selected Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Make pinning of ITLBs optionalChristophe Leroy2017-08-153-13/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As stated in a comment in head_8xx.S, today we "Always pin the first 8 MB ITLB to prevent ITLB misses while mucking around with SRR0/SRR1 in asm". This issue has just been cleared by the preceding patch, therefore we can make this pinning optional (on by default) and independent of DATA pinning. This patch also makes pinning of IMMR independent of pinning of DATA. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/32: Avoid risk of unrecoverable TLBmiss inside entry_32.SChristophe Leroy2017-08-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default, the 8xx pins an ITLB on the first 8M of memory in order to avoid any ITLB miss on kernel code. However, with some debug functions like DEBUG_PAGEALLOC and DEBUG_RODATA, pinning TLBs is contradictory. In order to avoid any ITLB miss in a critical section without pinning TLBs, we have to ensure that there is no page boundary crossed between the setup of a new value in SRR0/SRR1 and the associated RFI. The functions modifying srr0/srr1 are all located in setup_32.S. They are spread over almost 4kbytes. The patch forces a 12 bits (4kbytes) alignment for those functions. This garanties that the functions remain in a single 4k page. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Remove macro that checks kernel addressChristophe Leroy2017-08-151-13/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macro to check if an address is a kernel address or not is not used anymore in DTLBmiss handler. It is used in ITLB miss handler and in DTLB error handler. DTLB error handler is not a hot path, it doesn't need such optimisation. In order to simplify a following patch which will rework ITLB miss handler, we remove the macros and reintroduce them inside the handler. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Ensures RAM mapped with LTLB is seen as block mapped on 8xx.Christophe Leroy2017-08-151-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the 8xx, the RAM mapped with LTLBs must be seen as block mapped, just like areas mapped with BATs on standard PPC32. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/chrp: Store the intended structureJulia Lawall2017-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally the values in the resource field and the argument to ARRAY_SIZE in the num_resources are the same. In this case, the value in the reousrce field is the same as the one in the previous platform_device structure, and appears to be a copy-paste error. Replace the value in the resource field with the argument to the local call to ARRAY_SIZE. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/l2cr_6xx: Fix invalid use of register expressionsAndreas Schwab2017-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes another invalid use of register expressions. Signed-off-by: Andreas Schwab <schwab@linux-m68k.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/iommu: Avoid undefined right shift in iommu_range_alloc()Michael Ellerman2017-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In iommu_range_alloc() we generate a mask by right shifting ~0, however if the specified alignment is 0 then we right shift by 64, which is undefined. UBSAN tells us so: UBSAN: Undefined behaviour in ../arch/powerpc/kernel/iommu.c:193:35 shift exponent 64 is too large for 64-bit type 'long unsigned int' We can avoid it by instead generating the mask with: align_mask = (1ull << align_order) - 1; That will also generate an undefined shift if align_order is 64 or greater, but that shouldn't be a problem for a while. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/perf/imc: Fix nest events on muti socket systemAnju T2017-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In a multi node system with discontiguous node ids, nest event values are not showing up properly. eg. lscpu output: NUMA node0 CPU(s): 0-15 NUMA node8 CPU(s): 16-31 Nest event values on such systems can be counted on CPUs <= 15: $./perf stat -e 'nest_powerbus0_imc/PM_PB_CYC/' -C 0-14 -I 1000 sleep 1000 # time counts unit events 1.000294577 30,17,24,42,880 nest_powerbus0_imc/PM_PB_CYC/ But not on CPUs >= 16: $./perf stat -e 'nest_powerbus0_imc/PM_PB_CYC/' -C 16-28 -I 1000 sleep 1000 # time counts unit events 1.000049902 <not supported> nest_powerbus0_imc/PM_PB_CYC/ This is because, when fetching the reference count, the node id (which may be sparse) is used as the array index, not the node number (which is 0 based and contiguous). Fix it by using the node number as the array index. $./perf stat -e 'nest_powerbus0_imc/PM_PB_CYC/' -C 16-28 -I 1000 sleep 1000 # time counts unit events 1.000241961 26,12,35,28,704 nest_powerbus0_imc/PM_PB_CYC/ Signed-off-by: Anju T Sudhakar <anju@linux.vnet.ibm.com> [mpe: Change log tweaks for clarity and brevity] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/mm/nohash: Move definition of PGALLOC_GFP to fix build errorsMichael Ellerman2017-08-152-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some obscure Book3E configs (randconfig) we can end up missing a definition for PGALLOC_GFP in pgtable_64.c. Fix it by moving the definition to asm/pgalloc.h. Fixes: de3b87611dd1 ("powerpc/mm/book(e)(3s)/64: Add page table accounting") Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/xmon: Exclude all of xmon from ftraceNaveen N. Rao2017-08-152-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exclude core xmon files from ftrace (along with an xmon xive helper outside of xmon/) to minimize impact of ftrace while within xmon. Before: /sys/kernel/debug/tracing# grep -ci xmon available_filter_functions 26 After: /sys/kernel/debug/tracing# grep -ci xmon available_filter_functions 0 Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> [mpe: Use $(subst ..) on KBUILD_CFLAGS rather than CFLAGS_REMOVE_xxx] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/xmon: Disable tracing when entering xmonBreno Leitao2017-08-141-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If tracing is enabled and you get into xmon, the tracing buffer continues to be updated, causing possible loss of data and unnecessary tracing information coming from xmon functions. This patch simple disables tracing when entering xmon, and re-enables it if the kernel is resumed (with 'x'). Signed-off-by: Breno Leitao <leitao@debian.org> Acked-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/xmon: Dump ftrace buffers for the current CPU onlyBreno Leitao2017-08-141-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current xmon 'dt' command dumps the tracing buffer for all the CPUs, which makes it very hard to read due to the fact that most of powerpc machines currently have many CPUs. Other than that, the CPU lines are interleaved in the ftrace log. This new option just dumps the ftrace buffer for the current CPU. Signed-off-by: Breno Leitao <leitao@debian.org> Acked-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | drivers/macintosh: Make wf_control_ops and wf_pid_param constBhumika Goyal2017-08-143-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make wf_control_ops const as they are only stored in the ops field of a wf_control structure, which is const. Make wf_pid_param const as they are only used during a copy operation. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/perf: Fix double unlock in imc_common_cpuhp_mem_free()Dan Carpenter2017-08-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function is not called with the nest_init_lock held, and it also unlocks the nest_init_lock immediately below, so it's fairly clear that this is a typo and should be locking the lock. Fixes: 885dcd709ba9 ("powerpc/perf: Add nest IMC PMU support") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Fix two CONFIG_8xx left behindChristophe Leroy2017-08-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 968159c0031ac ("powerpc/8xx: Getting rid of remaining use of CONFIG_8xx") removed all but 2 references to 8xx in Kconfigs. This patch removes the two remaining ones. Fixes: 968159c0031a ("powerpc/8xx: Getting rid of remaining use of CONFIG_8xx") Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/xive: Fix section mismatch warningsMichael Ellerman2017-08-102-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Both xive_core_init() and xive_native_init() are called from and call __init routines, so they should also be __init. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/mm: Fix section mismatch warning in early_check_vec5()Michael Ellerman2017-08-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | early_check_vec5() is called from and calls __init routines, so should also be __init. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Remove cpu dependent macro instructions from head_8xxChristophe Leroy2017-08-101-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | head_8xx is dedicated to 8xx so no need to use macros that depends on the CPU Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Use symbolic names for DSISR bits in DSIChristophe Leroy2017-08-102-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use symbolic names for DSISR bits in DSI Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Use symbolic PVR valueChristophe Leroy2017-08-102-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the 8xx, PVR values defined in arch/powerpc/include/asm/reg.h are nowhere used. Remove all defines and add PVR_8xx Use it in arch/powerpc/kernel/cputable.c Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: remove CONFIG_8xxChristophe Leroy2017-08-101-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two config options exist to define powerpc MPC8xx: * CONFIG_PPC_8xx * CONFIG_8xx arch/powerpc/platforms/Kconfig.cputype has contained the following comment about CONFIG_8xx item for some years: "# this is temp to handle compat with arch=ppc" There is no more users of CONFIG_8xx, so remove it. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Getting rid of remaining use of CONFIG_8xxChristophe Leroy2017-08-1020-33/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two config options exist to define powerpc MPC8xx: * CONFIG_PPC_8xx * CONFIG_8xx arch/powerpc/platforms/Kconfig.cputype has contained the following comment about CONFIG_8xx item for some years: "# this is temp to handle compat with arch=ppc" arch/powerpc is now the only place with remaining use of CONFIG_8xx: get rid of them. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/kconfig: Simplify PCI_QSPAN selectionChristophe Leroy2017-08-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4xx, CPM2 and 8xx cannot be selected at the same time, so no need to test 8xx && !4xx && !CPM2. Testing 8xx is enough. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/time: refactor MFTB() to limit number of ifdefsChristophe Leroy2017-08-105-35/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 8xx cannot access the TBL and TBU registers using mfspr/mtspr It must be accessed using mftb/mftbu Due to this, there is a number of places with #ifdef CONFIG_8xx This patch defines new macros MFTBL(x) and MFTBU(x) on the same model as MFTB(x) and tries to make use of them as much as possible. In arch/powerpc/include/asm/timex.h, we also remove the ifdef for the asm() operands as the compiler doesn't mind unused operands Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Move mpc8xx_pic.c from sysdev to platform/8xxChristophe Leroy2017-08-105-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | mpc8xx_pic.c is dedicated to the 8xx, so move it to platform/8xx Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/cpm1: link to CONFIG_CPM1 instead of CONFIG_8xxChristophe Leroy2017-08-103-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To remain consistent with what is done with CPM2, let's link CPM1 related parts to CONFIG_CPM1 instead of CONFIG_8xx When something depends on both CPM1 and CPM2 we associate it with CONFIG_CPM Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Remove SoftwareEmulation()Christophe Leroy2017-08-102-19/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit aa42c69c67f82 ("[POWERPC] Add support for FP emulation for the e300c2 core"), program_check_exception() can be called for math emulation. In that case, 'reason' is 0. On the 8xx, there is a Software Emulation interrupt which is called for all unimplemented and illegal instructions. This interrupt calls SoftwareEmulation() which does almost the same as program_check_exception() called with reason = 0. The Software Emulation interrupt sets all reason bits to 0, it is therefore possible to call program_check_exception() directly from the interrupt handler. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Move 8xx machine check handlers into platforms/8xxChristophe Leroy2017-08-103-26/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the same spirit as what was done for 4xx and 44x, move the 8xx machine check into platforms/8xx Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/8xx: Simplify CONFIG_8xx checks in MakefileChristophe Leroy2017-08-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The entire 8xx directory is omitted if CONFIG_8xx is not enabled, so within the 8xx/Makefile CONFIG_8xx is always y. So convert obj-$(CONFIG_8xx) to the more obvious obj-y. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/traps: Use SRR1 defines for program check reasonsMichael Ellerman2017-08-102-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we open code the reason codes for program checks. Instead use the existing SRR1 defines. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/mce: Move 64-bit machine check code into mce.cMichael Ellerman2017-08-102-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We already have mce.c which is built for 64bit and contains other parts of the machine check code, so move these bits in there too. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/traps: machine_check_generic() is only used on 32-bitMichael Ellerman2017-08-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it clear that the fallback version of machine_check_generic() is only used on 32-bit configs. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/traps: Inline get_mc_reason()Michael Ellerman2017-08-101-10/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | get_mc_reason() no longer provides (if it ever really did) any meaningful abstraction, so remove it. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/4xx: Move machine_check_4xx() into platforms/4xxMichael Ellerman2017-08-103-18/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have 4xx platform directory we can move the 4xx machine check handler in there. Again we drop get_mc_reason() and replace it with regs->dsisr directly (which is actually SPRN_ESR). Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/4xx: Create 4xx pseudo-platform in platforms/4xxMichael Ellerman2017-08-1012-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a lot of code in sysdev for supporting 4xx, ie. either 40x or 44x. Instead it would be cleaner if it was all in platforms/4xx. This is slightly odd in that we don't actually define any machines in the 4xx platform, as is usual for a platform directory. But still it seems like a better result to have all this related code in a directory by itself. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/44x: Move 44x machine check handlers into platforms/44xMichael Ellerman2017-08-103-75/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have several 44x machine check handlers defined in traps.c. It would be preferable if they were split out with the platforms that use them. Do that. In the process, drop get_mc_reason() and instead just open code the lookup of reason from regs->dsisr. This avoids a pointless layer of abstraction. We know to use regs->dsisr because 44x enables BOOKE which enables PPC_ADV_DEBUG_REGS, and FSL_BOOKE is not enabled on 44x builds. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/44x: Simplify CONFIG_44x checks in MakefileMichael Ellerman2017-08-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The entire 44x directory is omitted if CONFIG_44x is not enabled, so within the 44x/Makefile CONFIG_44x is always y. So convert obj-$(CONFIG_44x) to the more obvious obj-y. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/47x: Guard 47x cputable entries with CONFIG_PPC_47xMichael Ellerman2017-08-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we build the 47x cputable entries even when CONFIG_PPC_47x is disabled. That means a kernel built without CONFIG_PPC_47x will claim to support a 47x CPU and start booting, only to break somewhere later because it doesn't have 47x support compiled in. So guard the 47x cputable entries with CONFIG_PPC_47x. Note that this is inside the #ifdef CONFIG_44x section, because 47x depends on 44x. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/powernv: Add support to clear sensor groups dataShilpasri G Bhat2017-08-107-1/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds support for clearing different sensor groups. OCC inband sensor groups like CSM, Profiler, Job Scheduler can be cleared using this driver. The min/max of all sensors belonging to these sensor groups will be cleared. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/powernv: Add support to set power-shifting-ratioShilpasri G Bhat2017-08-107-1/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to set power-shifting-ratio which hints the firmware how to distribute/throttle power between different entities in a system (e.g CPU v/s GPU). This ratio is used by OCC for power capping algorithm. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/powernv: Add support for powercap frameworkShilpasri G Bhat2017-08-107-1/+290
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds a generic powercap framework to change the system powercap inband through OPAL-OCC command/response interface. Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/pseries: Don't print failure message in energy driverNicholas Piggin2017-08-101-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver currently reports the H_BEST_ENERGY hypervisor call is unsupported (even when booting in a non-virtualised environment). This is not something the administrator can do much with, and not significant for debugging. Remove it. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/lib/sstep: Add isel instruction emulationMatt Brown2017-08-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds emulation for the isel instruction. Tested for correctness against the isel instruction and its extended mnemonics (lt, gt, eq) on ppc64le. Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
* | | | powerpc/lib/sstep: Add prty instruction emulationMatt Brown2017-08-101-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds emulation for the prtyw and prtyd instructions. Tested for logical correctness against the prtyw and prtyd instructions on ppc64le. Signed-off-by: Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by: Cyril Bur <cyrilbur@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-10 17:51:00 +0000