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* Merge tag 'cxl-for-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds2022-08-1039-576/+5498
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| * cxl/hdm: Fix skip allocations vs multiple pmem allocationsDan Williams2022-08-051-1/+10
| * cxl/region: Disallow region granularity != window granularityDan Williams2022-08-051-6/+7
| * cxl/region: Fix x1 interleave to greater than x1 interleave routingDan Williams2022-08-051-1/+5
| * cxl/region: Move HPA setup to cxl_region_attach()Dan Williams2022-08-052-26/+24
| * cxl/region: Fix decoder interleave programmingDan Williams2022-08-051-0/+3
| * Documentation: cxl: remove dangling kernel-doc referenceBagas Sanjaya2022-08-051-3/+0
| * cxl/region: describe targets and nr_targets members of cxl_region_paramsBagas Sanjaya2022-08-051-0/+2
| * cxl/regions: add padding for cxl_rr_ep_add nested listsBagas Sanjaya2022-08-051-0/+3
| * cxl/region: Fix IS_ERR() vs NULL checkDan Carpenter2022-08-051-2/+2
| * cxl/region: Fix region reference target accountingDan Williams2022-08-051-28/+43
| * cxl/region: Fix region commit uninitialized variable warningDan Williams2022-08-051-17/+13
| * cxl/region: Fix port setup uninitialized variable warningsDan Williams2022-08-051-3/+22
| * cxl/region: Stop initializing interleave granularityDan Williams2022-08-011-4/+0
| * cxl/hdm: Fix DPA reservation vs cxl_endpoint_decoder lifetimeDan Williams2022-08-011-2/+5
| * cxl/acpi: Minimize granularity for x1 interleavesDan Williams2022-08-012-0/+8
| * cxl/region: Delete 'region' attribute from root decodersDan Williams2022-08-011-1/+2
| * cxl/acpi: Autoload driver for 'cxl_acpi' test devicesDan Williams2022-08-011-0/+7
| * cxl/region: decrement ->nr_targets on error in cxl_region_attach()Dan Carpenter2022-08-011-1/+3
| * cxl/region: prevent underflow in ways_to_cxl()Dan Carpenter2022-08-012-3/+4
| * cxl/region: uninitialized variable in alloc_hpa()Dan Carpenter2022-08-011-1/+1
| * powerpc/mm: Export memory_add_physaddr_to_nid() for modulesMichael Ellerman2022-07-291-0/+1
| * cxl/region: Introduce cxl_pmem_region objectsDan Williams2022-07-268-12/+446
| * cxl/pmem: Fix offline_nvdimm_bus() to offline by bridgeDan Williams2022-07-262-4/+18
| * cxl/region: Add region driver boiler plateDan Williams2022-07-264-1/+66
| * cxl/hdm: Commit decoder state to hardwareDan Williams2022-07-256-11/+486
| * cxl/region: Program target listsDan Williams2022-07-254-11/+259
| * cxl/region: Attach endpoint decodersDan Williams2022-07-255-12/+394
| * cxl/acpi: Add a host-bridge index lookup mechanismDan Williams2022-07-252-0/+18
| * cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams2022-07-256-2/+340
| * cxl/region: Allocate HPA capacity to regionsDan Williams2022-07-254-1/+183
| * cxl/region: Add interleave geometry attributesBen Widawsky2022-07-253-0/+188
| * cxl/region: Add a 'uuid' attributeBen Widawsky2022-07-253-0/+153
| * cxl/region: Add region creation supportBen Widawsky2022-07-219-0/+311
| * resource: Introduce alloc_free_mem_region()Dan Williams2022-07-213-35/+150
| * cxl/mem: Enumerate port targets before adding endpointsDan Williams2022-07-213-29/+47
| * cxl/hdm: Add sysfs attributes for interleave ways + granularityBen Widawsky2022-07-212-0/+50
| * cxl/port: Move dport tracking to an xarrayDan Williams2022-07-213-56/+47
| * cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams2022-07-212-34/+30
| * cxl/port: Record parent dport when adding portsDan Williams2022-07-214-20/+27
| * cxl/port: Record dport in endpoint referencesDan Williams2022-07-212-17/+37
| * cxl/hdm: Add support for allocating DPA to an endpoint decoderDan Williams2022-07-214-2/+295
| * cxl/hdm: Track next decoder to allocateDan Williams2022-07-213-0/+18
| * cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams2022-07-214-0/+55
| * cxl/hdm: Enumerate allocated DPADan Williams2022-07-213-11/+149
| * cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams2022-07-214-17/+48
| * cxl/core: Define a 'struct cxl_root_decoder'Dan Williams2022-07-213-13/+76
| * cxl/acpi: Track CXL resources in iomem_resourceDan Williams2022-07-213-3/+149
| * cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams2022-07-215-91/+191
| * Documentation/cxl: Use a double line break between entriesDan Williams2022-07-191-0/+16
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