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* Revert "Revert "drm/amdgpu: Add table_freed parameter to amdgpu_vm_bo_update""Eric Huang2021-08-024-10/+10
| | | | | | | | | This reverts commit 024d8811c90ed56d8b90cdcf71e51c9fedeff460. Revert reason: The issue has been resolved. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Revert "Revert "drm/amdkfd: Add heavy-weight TLB flush after unmapping""Eric Huang2021-08-021-0/+1
| | | | | | | | | This reverts commit 430f8e6edbaac8abfddf76f1aef732d9c6257211. Revert reason: Issue has been resolved. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/amdgpu: Fix out-of-bounds read when update mappingxinhui pan2021-08-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If one GTT BO has been evicted/swapped out, it should sit in CPU domain. TTM only alloc struct ttm_resource instead of struct ttm_range_mgr_node for sysMem. Now when we update mapping for such invalidated BOs, we might walk out of bounds of struct ttm_resource. Three possible fix: 1) Let sysMem manager alloc struct ttm_range_mgr_node, like ttm_range_manager does. 2) Pass pages_addr to update_mapping function too, but need memset pages_addr[] to zero when unpopulate. 3) Init amdgpu_res_cursor directly. bug is detected by kfence. ================================================================== BUG: KFENCE: out-of-bounds read in amdgpu_vm_bo_update_mapping+0x564/0x6e0 Out-of-bounds read at 0x000000008ea93fe9 (64B right of kfence-#167): amdgpu_vm_bo_update_mapping+0x564/0x6e0 [amdgpu] amdgpu_vm_bo_update+0x282/0xa40 [amdgpu] amdgpu_vm_handle_moved+0x19e/0x1f0 [amdgpu] amdgpu_cs_vm_handling+0x4e4/0x640 [amdgpu] amdgpu_cs_ioctl+0x19e7/0x23c0 [amdgpu] drm_ioctl_kernel+0xf3/0x180 [drm] drm_ioctl+0x2cb/0x550 [drm] amdgpu_drm_ioctl+0x5e/0xb0 [amdgpu] kfence-#167 [0x000000008e11c055-0x000000001f676b3e ttm_sys_man_alloc+0x35/0x80 [ttm] ttm_resource_alloc+0x39/0x50 [ttm] ttm_bo_swapout+0x252/0x5a0 [ttm] ttm_device_swapout+0x107/0x180 [ttm] ttm_global_swapout+0x6f/0x130 [ttm] ttm_tt_populate+0xb1/0x2a0 [ttm] ttm_bo_handle_move_mem+0x17e/0x1d0 [ttm] ttm_mem_evict_first+0x59d/0x9c0 [ttm] ttm_bo_mem_space+0x39f/0x400 [ttm] ttm_bo_validate+0x13c/0x340 [ttm] ttm_bo_init_reserved+0x269/0x540 [ttm] amdgpu_bo_create+0x1d1/0xa30 [amdgpu] amdgpu_bo_create_user+0x40/0x80 [amdgpu] amdgpu_gem_object_create+0x71/0xc0 [amdgpu] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x2f2/0xcd0 [amdgpu] kfd_ioctl_alloc_memory_of_gpu+0xe2/0x330 [amdgpu] kfd_ioctl+0x461/0x690 [amdgpu] Signed-off-by: xinhui pan <xinhui.pan@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge tag 'amd-drm-next-5.15-2021-07-29' of ↵Dave Airlie2021-07-30164-2662/+6856
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.15-2021-07-29: amdgpu: - VCN/JPEG power down sequencing fixes - Various navi pcie link handling fixes - Clockgating fixes - Yellow Carp fixes - Beige Goby fixes - Misc code cleanups - S0ix fixes - SMU i2c bus rework - EEPROM handling rework - PSP ucode handling cleanup - SMU error handling rework - AMD HDMI freesync fixes - USB PD firmware update rework - MMIO based vram access rework - Misc display fixes - Backlight fixes - Add initial Cyan Skillfish support - Overclocking fixes suspend/resume amdkfd: - Sysfs leak fix - Add counters for vm faults and migration - GPUVM TLB optimizations radeon: - Misc fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210730033455.3852-1-alexander.deucher@amd.com
| * drm/amd/pm: Fix a bug in semaphore double-lockLuben Tuikov2021-07-281-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a bug in smu_cmn_send_msg_without_waiting() in that this function does not need to take the smu->message_lock mutex in order to send a message down to the SMU. The mutex is acquired by the caller of this function instead. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Changfeng Zhu <Changfeng.Zhu@amd.com> Cc: Huang Rui <ray.huang@amd.com> Fixes: 5810323ba69289 ("drm/amd/pm: Fix a bug communicating with the SMU (v5)") Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: enable psp front door loading by default for cyan_skillfish2Huang Rui2021-07-281-3/+4
| | | | | | | | | | | | | | | | The function is ready on psp firmware, and enable it by default. Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: adjust fence driver enable sequenceLikun Gao2021-07-283-47/+14
| | | | | | | | | | | | | | | | | | | | | | Fence driver was enabled per ring when sw init on per IP block before. Change to enable all the fence driver at the same time after amdgpu_device_ip_init finished. Rename some function related to fence to make it reasonable for read. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Added PSP13 BL loading support for additional driversJohn Clements2021-07-281-0/+18
| | | | | | | | | | | | | | | | Added BL loading support for soc/intf/dbg drivers Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Consolidated PSP13 BL FW loadingJohn Clements2021-07-281-35/+11
| | | | | | | | | | | | | | | | Remove duplicate code Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Added support for added psp driver binaries FWJohn Clements2021-07-283-7/+70
| | | | | | | | | | | | | | | | Detect psp driver binaries packed into FW and try to load the FW Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Added latest PSP FW headerJohn Clements2021-07-282-21/+116
| | | | | | | | | | | | | | | | Improved handling for scalling PSP FW binaries Signed-off-by: John Clements <john.clements@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: remove the access of xxx_PSP_DEBUG on cycan_skillfishHuang Rui2021-07-281-2/+0
| | | | | | | | | | | | | | | | | | It won't need to clear the xxx_PSP_DEBUG registers, because firmware will handle this change. Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/display: add support for multiple backlightsAlex Deucher2021-07-283-71/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | On platforms that support multiple backlights, register each one separately. This lets us manage them independently rather than registering a single backlight and applying the same settings to both. v2: fix typo: Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * maintainers: add bugs and chat URLs for amdgpuSimon Ser2021-07-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | Add links to the issue tracker and the IRC channel for the amdgpu driver. Signed-off-by: Simon Ser <contact@emersion.fr> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Pan Xinhui <Xinhui.Pan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu/display: only enable aux backlight control for OLED panelsAlex Deucher2021-07-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've gotten a number of reports about backlight control not working on panels which indicate that they use aux backlight control. A recent patch: commit 2d73eabe2984a435737498ab39bb1500a9ffe9a9 Author: Camille Cho <Camille.Cho@amd.com> Date: Thu Jul 8 18:28:37 2021 +0800 drm/amd/display: Only set default brightness for OLED [Why] We used to unconditionally set backlight path as AUX for panels capable of backlight adjustment via DPCD in set default brightness. [How] This should be limited to OLED panel only since we control backlight via PWM path for SDR mode in LCD HDR panel. Reviewed-by: Krunoslav Kovac <krunoslav.kovac@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Camille Cho <Camille.Cho@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Changes some other code to only use aux for backlight control on OLED panels. The commit message seems to indicate that PWM should be used for SDR mode on HDR panels. Do something similar for backlight control in general. This may need to be revisited if and when HDR started to get used. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1438 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=213715 Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/pm: restore user customized OD settings properly for Sienna CichlidEvan Quan2021-07-281-9/+28
| | | | | | | | | | | | | | | | | | Properly restore those committed and non-committed user customized OD settings. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/pm: restore user customized OD settings properly for NV1xEvan Quan2021-07-285-17/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The customized OD settings can be divided into two parts: those committed ones and non-committed ones. - For those changes which had been fed to SMU before S3/S4/Runpm suspend kicked, they are committed changes. They should be properly restored and fed to SMU on S3/S4/Runpm resume. - For those non-committed changes, they are restored only without feeding to SMU. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * Revert "Revert "drm/amdkfd: Add memory sync before TLB flush on unmap""Eric Huang2021-07-281-3/+20
| | | | | | | | | | | | | | | | | | This reverts commit 4bba567c8c35a9cbcd16fb4780a0c3dfd162e08e. Revert reason: The issue has been resolved. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * Revert "Revert "drm/amdgpu: Fix warning of Function parameter or member not ↵Eric Huang2021-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | described"" This reverts commit 4e7b93ca52fb228b177168d436449c5671415a72. Revert reason: The issue has been resolved. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * Revert "Revert "drm/amdkfd: Make TLB flush conditional on mapping""Eric Huang2021-07-284-20/+27
| | | | | | | | | | | | | | | | | | This reverts commit 7ed9876c9793bfe96fed58ba645d6c8e32f26001. Revert reason: The issue has been resolved. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * Revert "Revert "drm/amdgpu: Add table_freed parameter to amdgpu_vm_bo_update""Eric Huang2021-07-284-10/+10
| | | | | | | | | | | | | | | | | | This reverts commit 024d8811c90ed56d8b90cdcf71e51c9fedeff460. Revert reason: The issue has been resolved. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * Revert "Revert "drm/amdkfd: Add heavy-weight TLB flush after unmapping""Eric Huang2021-07-281-0/+1
| | | | | | | | | | | | | | | | | | This reverts commit 430f8e6edbaac8abfddf76f1aef732d9c6257211. Revert reason: Issue has been resolved. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: 3.2.146Aric Cyr2021-07-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This version brings along following fixed: - Guard DST_Y_PREFETCH register overflow in DCN21 - Add missing DCN21 IP parameter - Fix PSR command version - Add ETW logging for AUX failures - Add ETW log to dmub_psr_get_state - Fixed EdidUtility build errors - Fix missing reg offset for the dmcub test debug registers - Adding update authentication interface - Remove unused functions of opm state query support - Always wait for update lock status - Refactor riommu invalidation wa - Ensure dentist display clock update finished in DCN20 Reviewed-by: Hsieh Mike <Mike.Hsieh@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Aric Cyr <aric.cyr@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: [FW Promotion] Release 0.0.76Anthony Koo2021-07-281-2/+2
| | | | | | | | | | | | | | | | Reviewed-by: Cyr Aric <aric.cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: ensure dentist display clock update finished in DCN20Dale Zhao2021-07-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] We don't check DENTIST_DISPCLK_CHG_DONE to ensure dentist display clockis updated to target value. In some scenarios with large display clock margin, it will deliver unfinished display clock and cause issues like display black screen. [How] Checking DENTIST_DISPCLK_CHG_DONE to ensure display clock has been update to target value before driver do other clock related actions. Reviewed-by: Cyr Aric <aric.cyr@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Dale Zhao <dale.zhao@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: refactor riommu invalidation waEric Yang2021-07-287-50/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] A cleaner solution, only done once on boot. [How] Remove previous workaround and configure an extra vmid one time on boot Reviewed-by: Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Always wait for update lock statusEric Bernstein2021-07-281-5/+3
| | | | | | | | | | | | | | | | | | | | | | Remove code that would skip wait for lock status for Diags FPGA case Reviewed-by: Laktyushkin Dmytro <dmytro.laktyushkin@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: remove unused functionsWenjing Liu2021-07-287-53/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | [why] It has been decided that opm state query support will be dropped. Therefore link encryption enabled and save current encryption states won't be used anymore and there are no foreseeable usages in the future. We will remove these two interfaces for clean up. Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: add update authentication interfaceWenjing Liu2021-07-282-6/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] Previously to toggle authentication, we need to remove and add the same display back with modified adjustment. This method will toggle DTM state without actual hardware changes. This is not per design and would cause potential issues in the long run. [how] We are creating a dedicated interface that does the same thing as remove and add back the display without changing DTM state. Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: fix missing reg offsetEric Yang2021-07-281-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Initializing was missing reg offsets for the dmcub test debug registers causing assert [How] Add initialization Reviewed-by: Kazlauskas Nicholas <Nicholas.Kazlauskas@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fixed EdidUtility build errorsMark Morra2021-07-284-320/+382
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [HOW] Added #ifdefs and refactored various parts of dc to allow dc_link to be built by AMD EDID UTILITY [WHY] dc_dsc was refactored moving some of the code that AMD EDID UTILITY needed to dc_link, so now dc_link needs to be included by AMD EDID UTILITY Squash in DCN config fix (Alex) Reviewed-by: Leung Martin <Martin.Leung@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Mark Morra <MarkAlbert.Morra@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Add ETW log to dmub_psr_get_stateWyatt Wood2021-07-271-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] GPINT commands have the lowest priority in DMCUB, so it's possible that the command isn't processed in time. [How] Add a log to help identify this case. Reviewed-by: Koo Anthony <Anthony.Koo@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Add ETW logging for AUX failuresWyatt Wood2021-07-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Would like to identify the cause of AUX transactions failing via ETW logs. [How] Add ETW logging for AUX failures. Reviewed-by: Pavic Josip <Josip.Pavic@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Wyatt Wood <wyatt.wood@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fix PSR command versionMikita Lipski2021-07-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] For dual eDP when setting the new settings we need to set command version to DMUB_CMD_PSR_CONTROL_VERSION_1, otherwise DMUB will not read panel_inst parameter. [how] Instead of PSR_VERSION_1 pass DMUB_CMD_PSR_CONTROL_VERSION_1 Reviewed-by: Wood Wyatt <Wyatt.Wood@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Add missing DCN21 IP parameterVictor Lu2021-07-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] IP parameter min_meta_chunk_size_bytes is read for bandwidth calculations but it was never defined. [how] Define min_meta_chunk_size_bytes and initialize value to 256. Reviewed-by: Laktyushkin Dmytro <dmytro.laktyushkin@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Rename amdgpu_acpi_is_s0ix_supportedPratik Vishwakarma2021-07-273-6/+6
| | | | | | | | | | | | | | | | | | Rename amdgpu_acpi_is_s0ix_supported to better explain functionality by renaming to amdgpu_acpi_is_s0ix_active Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Guard DST_Y_PREFETCH register overflow in DCN21Victor Lu2021-07-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [why] DST_Y_PREFETCH can overflow when DestinationLinesForPrefetch values are too large due to the former being limited to 8 bits. [how] Set the maximum value of DestinationLinesForPrefetch to be 255 * refclk period. Reviewed-by: Laktyushkin Dmytro <dmytro.laktyushkin@amd.com> Acked-by: Solomon Chiu <solomon.chiu@amd.com> Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Check pmops for desired suspend statePratik Vishwakarma2021-07-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] User might change the suspend behaviour from OS. [How] Check with pm for target suspend state and set s0ix flag only for s2idle state. v2: User might change default suspend state, use target state v3: squash in build fix Suggested-by: Lijo Lazar <Lijo.Lazar@amd.com> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: retire sdma v5_2 golden settings from driverHawking Zhang2021-07-231-17/+0
| | | | | | | | | | | | | | | | | | | | They are initalized by hardware during power up phase, starting from sdma v5_2 generation Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Add msix restore for pass-through modeChengzhe Liu2021-07-231-1/+1
| | | | | | | | | | | | | | | | | | | | In pass-through mode, after mode 1 reset, msix enablement status would lost and never receives interrupt again. So, we should restore msix status after mode 1 reset. Signed-off-by: Chengzhe Liu <ChengZhe.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Change the imprecise outputRoy Sun2021-07-231-3/+3
| | | | | | | | | | | | | | | | The fail reason is that the vfgate is disabled Signed-off-by: Roy Sun <Roy.Sun@amd.com> Reviewed-by: Peng Ju Zhou <PengJu.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/display: Fix ASSR regression on embedded panelsStylon Wang2021-07-231-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Regression found in some embedded panels traces back to the earliest upstreamed ASSR patch. The changed code flow are causing problems with some panels. [How] - Change ASSR enabling code while preserving original code flow as much as possible - Simplify the code on guarding with internal display flag Bug: https://bugzilla.kernel.org/show_bug.cgi?id=213779 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1620 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: Clear doorbell interrupt status for Sienna CichlidChengzhe Liu2021-07-233-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On Sienna Cichlid, in pass-through mode, if we unload the driver in BACO mode(RTPM), then the kernel would receive thousands of interrupts. That's because there is doorbell monitor interrupt on BIF, so KVM keeps injecting interrupts to the guest VM. So we should clear the doorbell interrupt status after BACO exit. v2: Modify coding style and commit message Signed-off-by: Chengzhe Liu <ChengZhe.Liu@amd.com> Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amd/pm: Fix a bug communicating with the SMU (v5)Luben Tuikov2021-07-232-47/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a bug which if we probe a non-existing I2C device, and the SMU returns 0xFF, from then on we can never communicate with the SMU, because the code before this patch reads and interprets 0xFF as a terminal error, and thus we never write 0 into register 90 to clear the status (and subsequently send a new command to the SMU.) It is not an error that the SMU returns status 0xFF. This means that the SMU executed the last command successfully (execution status), but the command result is an error of some sort (execution result), depending on what the command was. When doing a status check of the SMU, before we send a new command, the only status which precludes us from sending a new command is 0--the SMU hasn't finished executing a previous command, and 0xFC--the SMU is busy. This bug was seen as the following line in the kernel log, amdgpu: Msg issuing pre-check failed(0xff) and SMU may be not in the right state! when subsequent SMU commands, not necessarily related to I2C, were sent to the SMU. This patch fixes this bug. v2: Add a comment to the description of __smu_cmn_poll_stat() to explain why we're NOT defining the SMU FW return codes as macros, but are instead hard-coding them. Such a change, can be followed up by a subsequent patch. v3: The changes are, a) Add comments to break labels in __smu_cmn_reg2errno(). b) When an unknown/unspecified/undefined result is returned back from the SMU, map that to -EREMOTEIO, to distinguish failure at the SMU FW. c) Add kernel-doc to smu_cmn_send_msg_without_waiting(), smu_cmn_wait_for_response(), smu_cmn_send_smc_msg_with_param(). d) In smu_cmn_send_smc_msg_with_param(), since we wait for completion of the command, if the result of the completion is undefined/unknown/unspecified, we print that to the kernel log. v4: a) Add macros as requested, though redundant, to be removed when SMU consolidates for all ASICs--see comment in code. b) Get out if the SMU code is unknown. v5: Rename the macro names. Cc: Alex Deucher <Alexander.Deucher@amd.com> Cc: Evan Quan <evan.quan@amd.com> Cc: Lijo Lazar <Lijo.Lazar@amd.com> Fixes: fcb1fe9c9e0031 ("drm/amd/powerplay: pre-check the SMU state before issuing message") Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alex Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: add pci device id for cyan_skillfishTao Zhou2021-07-231-0/+3
| | | | | | | | | | | | Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: add autoload_supported check for RLC autoloadLang Yu2021-07-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Asic cyan_skilfish2 won't support RLC autoload when using front door loading. We just use PSP to load firmware like gfx9 here. So add autoload_supported flag check instead of just checking firmware load type for RLC autoload. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: enable SMU for cyan_skilfishLang Yu2021-07-232-8/+13
| | | | | | | | | | | | | | | | | | | | Enable SMU support for cyan_skilfish. v2: Squash in fix (Alex) Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: add check_fw_version support for cyan_skillfishLang Yu2021-07-233-0/+5
| | | | | | | | | | | | | | | | Add check_fw_version function support for cyan_skillfish. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: add basic ppt functions for cyan_skilfishLang Yu2021-07-233-0/+105
| | | | | | | | | | | | | | | | Add basic ppt funcs support or cyan_skilfish. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/amdgpu: add smu interface header for cyan_skilfishLang Yu2021-07-231-0/+95
| | | | | | | | | | | | | | | | Add smu11_driver_if_cyan_skillfish.h for cyan_skilfish. Signed-off-by: Lang Yu <Lang.Yu@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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